Approximating functions

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First Claim
1. A binary logic circuit for approximating a mathematical function over a predefined range as a series of linear segments, each linear segment having a gradient and a base value, the binary logic circuit comprising:
 an input for receiving an input variable in the predefined range;
a plurality of logic chains each comprising;
a binary multiplier configured to perform multiplication by a gradient, anda binary adder configured to add a base value to an input or output of the binary multiplier; and
selection logic configured to select one of the logic chains in dependence on the input variable so as to provide, for the received input variable, an approximate value of the mathematical function,wherein each of the gradients has a minimum extended Hamming weight which is less than or equal to a threshold value.
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Abstract
A binary logic circuit for approximating a mathematical function over a predefined range as a series of linear segments, each linear segment having one of a predetermined set of fixed gradients and a corresponding base value, the binary logic circuit comprising: an input for receiving an input variable in the predefined range; a plurality of logic chains each comprising: a binary multiplier adapted to perform multiplication by a respective one of the set of fixed gradients using h−1 binary adders, where h is the extended Hamming weight; and a binary adder adapted to add a base value to the input or output of the binary multiplier; and selection logic configured to select one of the logic chains in dependence on the input variable so as to provide, for the received input variable, an approximate value of the mathematical function.
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20 Claims
 1. A binary logic circuit for approximating a mathematical function over a predefined range as a series of linear segments, each linear segment having a gradient and a base value, the binary logic circuit comprising:
an input for receiving an input variable in the predefined range; a plurality of logic chains each comprising; a binary multiplier configured to perform multiplication by a gradient, and a binary adder configured to add a base value to an input or output of the binary multiplier; and selection logic configured to select one of the logic chains in dependence on the input variable so as to provide, for the received input variable, an approximate value of the mathematical function, wherein each of the gradients has a minimum extended Hamming weight which is less than or equal to a threshold value.  View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
 16. A method of deriving a hardware representation of a binary logic circuit configured to approximate a mathematical function over a predefined range as a series of linear segments, the method comprising:
fitting a plurality of linear segments to the function over the predefined range, each linear segment having a gradient and a base value; and deriving a hardware representation for a binary logic circuit which comprises for each of the plurality of linear segments; a binary multiplier configured to perform multiplication by the gradient of the segment, and a binary adder configured to add the base value for the segment to an input or output of the binary multiplier; and selection logic configured to select, for a given input variable in the predefined range, one of the plurality of binary multipliers; wherein each of the gradients has a minimum extended Hamming weight which is less than or equal to a threshold value.  View Dependent Claims (17, 18, 19)
 20. A method of manufacturing a binary logic circuit in accordance with a hardware representation derived using an approximation of a mathematical function over a predefined range as a series of linear segments, comprising the steps of:
fitting a plurality of linear segments to the function over the predefined range, each linear segment having a gradient and a base value; and deriving a hardware representation for a binary logic circuit which comprises; for each of the plurality of linear segments; a binary multiplier configured to perform multiplication by the gradient of the segment, and a binary adder configured to add the base value for the segment to an input or output of the binary multiplier; and selection logic configured to select, for a given input variable in the predefined range, one of the plurality of binary multipliers; wherein each of the gradients has a minimum extended Hamming weight which is less than or equal to a threshold value.
1 Specification
This invention relates to a binary logic circuit for approximating a mathematical curve over a predefined range as a series of linear segments, and a method of deriving a hardware representation of such a binary logic circuit.
It is often desirable to perform certain functions at high speed in hardware. For example, integrated circuits for performing computer graphics processing and digital signal processing can frequently need to calculate the value of a log or gamma function for a given input value. Hardware for performing such calculations will typically operate over a defined range of input values and will typically be required to calculate the function to a certain level of accuracy. This allows hardware designers to use an approximation to a given function so as to provide a low latency solution which does not consume an inordinate amount of area on an integrated circuit.
The log_{2 }function is one such function which is often implemented in silicon and, conventionally, has often been approximated over the interval [1, 2] by a straight line. This is the socalled Mitchell approximation 102 illustrated in
The poor accuracy of the Mitchell approximation has led to the development of lookup table based approaches, such as is described in U.S. Pat. No. 4,583,180. These approaches replace the calculation of an approximation function (such as the straight line of Mitchell) with a lookup into a large table of precalculated values for the function itself. Such an approach is accurate but the memory requirements for the lookup table consume a large area of integrated circuit and can be relatively slow.
Further refinements of the lookup table approach have been developed which use interpolation between values in a smaller lookup table to provide a similar degree of accuracy whilst reducing the size of the table. One recent approach of this variety has been proposed by Paul et al. in their paper “A fast hardware approach for approximate, efficient logarithm and antilogarithm computations”, IEEE Transactions on VLSI Systems, Vol. 17, No. 2, February 2009. However, this approach requires the use of a multiplication array in hardware which is adapted to perform multiplication of two variables. Such a construct is complex and consumes a large area on an integrated circuit.
According to a first aspect of the present invention there is provided a binary logic circuit for approximating a mathematical function over a predefined range as a series of linear segments, each linear segment having one of a predetermined set of fixed gradients and a corresponding base value, the binary logic circuit comprising:
 an input for receiving an input variable in the predefined range;
 a plurality of logic chains each comprising:
 a binary multiplier adapted to perform multiplication by a respective one of the set of fixed gradients using h−1 binary adders, where h is the minimum Hamming weight of:
 a binary representation of the fixed gradient;
 a trinary representation of the fixed gradient; and
 a representation of the fixed gradient as a product of two binary numbers, two trinary numbers, or a binary and a trinary number;
 the h−1 binary adders being logically configured to perform the multiplication using the representation of the fixed gradient having that minimum Hamming weight h; and
 a binary adder adapted to add a base value to the input or output of the binary multiplier; and
 a binary multiplier adapted to perform multiplication by a respective one of the set of fixed gradients using h−1 binary adders, where h is the minimum Hamming weight of:
 selection logic configured to select one of the logic chains in dependence on the input variable so as to provide, for the received input variable, an approximate value of the mathematical function.
Each of the fixed gradients in the predetermined set of fixed gradients may have a minimum Hamming weight, h, which is less than or equal to a threshold value, wherein the threshold value determines a limit on the number of adders that the binary multiplier is adapted to use for performing a multiplication.
The threshold value may be 2 or 3.
The minimum Hamming weight h may be less than or equal to 3.
The selection logic may be configured to select one of the logic chains by comparing the received input variable to a predetermined set of break values, each break value representing a value of the input variable delimiting one or more linear segments.
The selection logic may be configured to determine a pair of adjacent break values between which the received input variable lies and, responsive to that determination, select the logic chain corresponding to the linear segment lying between that pair of adjacent break values.
Each of the set of break values may be used in the selection logic in the form of:
 a binary representation of the break value;
 a trinary representation of the break value; or
 a representation of the break value as a product of two binary numbers, two trinary numbers, or a binary and a trinary number;
the form used for each break value being the representation of that break value having the minimum Hamming weight.
The minimum Hamming weight of each of the set of break values may be less than or equal to 3.
The mathematical function may be expressed in the form y=f(x), where x and y represent values along respective Cartesian axes.
The binary adder of each logic chain may be arranged to add the respective base value to the output of the binary multiplier.
Each linear segment may represent part of a line that crosses the y axis at the base value.
The binary adder of each logic chain may be arranged to add the respective base value to the received input variable.
Each linear segment may represent part of a line that crosses the x axis at the base value.
The plurality of binary multipliers may comprise at least three binary multipliers.
The mathematical function may be a continuous smooth function over the predefined range.
The mathematical function may be a base 2 logarithm and the predefined range can be between 1 and 2.
The mathematical function may be a gamma function and the predefined range can be between 0 and 1.
The at least one of the plurality of logic chains may comprise a binary multiplier adapted to perform multiplication by a fixed gradient having a minimum hamming weight of greater than one.
Machine readable code may be provided for generating the binary logic circuit. A machine readable storage medium having encoded thereon nontransitory machine readable code may be provided for generating the binary logic circuit.
According to a second aspect of the present invention there is provided a method of deriving a hardware representation of a binary logic circuit configured to approximate a mathematical function over a predefined range as a series of linear segments, the method comprising:
 fitting a plurality of linear segments to the function over the predefined range, each segment extending between a pair of break points and having a fixed gradient selected from a predetermined set of fixed gradients,
 determining a base value for each of the segments; and
 deriving a hardware representation for a binary logic circuit which comprises:
 for each of the plurality of linear segments:
 a binary multiplier adapted to perform multiplication by the selected fixed gradient of the segment using h−1 binary adders, where h is the minimum Hamming weight of:
 a binary representation of the fixed gradient;
 a trinary representation of the fixed gradient; and
 a representation of the fixed gradient as a product of two binary numbers, two trinary numbers, or a binary and a trinary number;
 wherein the h−1 binary adders are logically configured to perform multiplication using the representation of the fixed gradient having the minimum Hamming weight h; and
 a binary adder adapted to add the determined base value to the input or output of the binary multiplier;
 and
 selection logic adapted to select, for a given input variable in the predefined range, one of the plurality of binary multipliers in dependence on the determined break points.
Each of the fixed gradients in the predetermined set of fixed gradients may have a minimum Hamming weight, h, which is less than or equal to a threshold value, wherein the threshold value determines a limit on the number of adders that the binary multiplier is adapted to use for performing a multiplication.
The threshold value may be 2 or 3.
The minimum Hamming weight h may be less than or equal to 3.
The method may further comprise:
 for each of the plurality of linear segments, calculating an average gradient between the break points delineating that linear segment; and
 selecting the closest fixed gradient to the calculated average gradient from the predetermined set of fixed gradients, the set of fixed gradients comprising gradients which are represented as binary representations, trinary representations and representations being the product of two binary numbers, two trinary numbers, or a binary and a trinary number.
The method may further comprise selecting a sufficient number of the plurality of linear segments such that the binary logic circuit achieves at least a predetermined accuracy substantially over the predefined range of values for the input variable.
The hardware representation may be RTL, a hardware description language, or a gatelevel description language.
The hardware description language may be Verilog or VDHL.
The gatelevel description language may be OASIS or GDSII.
Machine readable code may be provided for implementing the method of deriving a hardware representation of a binary logic circuit. A machine readable storage medium having encoded thereon nontransitory machine readable code may be provided for implementing the method of deriving a hardware representation of a binary logic circuit.
A data processing device is provided for generating a hardware representation according to the abovedescribed method.
A method of manufacturing a binary logic circuit in accordance with a hardware representation derived using the abovedescribed method is also provided.
The present invention will now be described by way of example with reference to the accompanying drawings. In the drawings:
The following description is presented by way of example to enable any person skilled in the art to make and use the invention. The present invention is not limited to the embodiments described herein and various modifications to the disclosed embodiments will be readily apparent to those skilled in the art.
It would be useful to have binary logic capable of calculating a mathematical function at high speed to a desired level of precision and which makes more efficient use of integrated circuit area.
A binary logic circuit is provided for calculating an estimate of a function over a predefined range. The logic described herein is suitable for approximating a wide variety of functions, including but not limited to log or gamma functions.
An example of an approximation which the binary logic circuit of
In the example shown in
These gradients are advantageous because the binary integer expression of each gradient has a low Hamming weight of either 2 or 3. The simplicity of the gradients shown in the above table when expressed in binary can be appreciated by rewriting each gradient as a combination of powers of two:
1.3125=1+¼+ 1/16
1.0625=1+ 1/16
0.8125=½+¼+ 1/16=1−⅛− 1/16
Note that it is the number of terms of a binary value which are a 1 (rather than a 0) which is significant to the complexity of a hardware implementation of a multiplication operation in which that binary value is an operand. An exponent of a binary value can be expressed as a left/right shift of the terms by an appropriate number of binary significand places, which can be achieved through the use of appropriate connections in hardware. No logic is required to perform such a left/right shift.
Although the gradient, start and end points of each line segment could in principle be freely chosen when approximating a function with a series of line segments, selecting particular fixed values for the gradient of the line segments at design time can provide significant benefits when implementing the binary logic shown in
A hardware implementation of a multiplication operation using an operand of extended Hamming weight n requires n−1 adder/subtractor units. The multiplication by the product of two binary or trinary numbers having extended Hamming weights m and n thus requires m−1+n−1 adders/subtractor units, and is equivalent to multiplication by an operand of extended Hamming weight m+n−1.
Examples illustrating the extended Hamming weight of binary numbers include:
 The binary number 1.0001 has a Hamming weight of 2 and this is also its extended Hamming weight since the standard binary representation comprises the minimum number of nonzero symbols of the representation types (a)(c).
 The binary number 0.1111 has a Hamming weight of 4 but can be expressed more efficiently in trinary form as 1.0001 (i.e. 10.0001) which has a Hamming weight of 2. The extended Hamming weight of the binary number 0.1111 is therefore 2.
 The binary number 1101001 has a Hamming weight of 4 but can be expressed more efficiently as a product of two trinary numbers each having a Hamming weight of 2 as 100
1 ×10001 ; the extended Hamming weight of the binary number 1101001 is therefore 3.
Multiplication by a binary or trinary number having an extended Hamming weight of 2 can be logically implemented using a single adder/subtractor, and multiplication by a binary or trinary number having an extended Hamming weight of 3 can be logically implemented using two adders/subtractors. Multiplication by two binary or trinary numbers having extended Hamming weights of 2 can also be implemented using two adders/subtractors, hence consuming the same area of silicon as multiplication by a binary or trinary number having an extended Hamming weight of 3.
Selecting the gradient of each of the segments 303, 304 and 305 to be a binary value having a low extended Hamming weight ensures that multiplication operations by the fixed gradients can be efficiently implemented in hardware whilst still providing a good approximation to the subject function. Multiplication by a fixed gradient with an extended Hamming weight of h can be implemented by a multiplication array having h−1 rows, each representing an addition operation where the operand is shifted by an appropriate number of places. For low extended Hamming weights, such a binary multiplication array provides a compact implementation which consumes only a small area of integrated circuit and offers high performance.
Multipliers 203205 in
It has been found that an efficient approximation can be provided in hardware for a wide range of functions using line segments having fixed gradients with extended Hamming weights of less than or equal to 3. In other examples, the fixed gradients of the line segments of an approximation configured according to the principles taught herein can have extended Hamming weights of less than or equal to 2. Generally speaking, the lower the extended Hamming weight of a gradient, the more efficient a given multiplication array implementing multiplication by that gradient. The number of line segments can be balanced against the extended Hamming weight of each segment at design time in order to minimise the complexity of the hardware. Generally speaking, the accuracy of a given approximation can be improved by using a larger number of segments, each having a gradient selected from a set of gradients which are known to have low extended Hamming weights. This may be preferable to using line segments which more accurately match the function but whose gradients have larger extended Hamming weights. This is because the resulting hardware approximation may offer a better balance between accuracy and the demands of the hardware in terms of speed and the area of integrated circuit consumed. The demands on the hardware are particularly high when the integrated circuit is to be included in a mobile device because silicon area and power consumption may be very limited.
In
Each of the line segments shown in
An estimate of the function f(x) can be calculated by calculating “mx+c” for a given value of x using the fixed gradient and intersection values of the line segment corresponding to the input value x. Thus, in order to calculate an approximation to the function log_{2}(x) for a given value of x, first the value of x is compared to the break points (1, 1.25, 1.5 and 2) to determine which line segment is relevant for the input value, x. Then the output of the corresponding multiplier in
On receiving an input value x 202 lying in the defined range between 1 and 2, the selection unit 201 identifies which of the multipliers 203205 provides the appropriate calculation for the approximation. This can be achieved by comparing the input value x to the stored boundary values of the line segments so as to identify which of the line segments forms the approximation to the curve f(x) at the given value of x. For example, looking at
Typically, each of the line segments will belong to a line which does not pass through the origin—i.e. has a nonzero intersection value c. This can be accommodated through the use of adders 210212 preceding the multiplier arrays or through the use of adders 207209 following the multiplier arrays that shift the inputs or outputs of the multiplier arrays by a set of base values, as shown in
Thus, to continue the example relating to the line segment 304, configuring adder 211 prior to multiplier 204 to add the value −1/1.0625=−0.941176 to input value x prior to its multiplication by the fixed gradient m would achieve the same result as employing adder 208 after the multiplier. It will be appreciated that other arrangements are possible to achieve the same result, including making use of adders both before and after a multiplier so as to modify x prior to its multiplication by a fixed gradient and to add a value to the result of that multiplication in order to provide a final output 211.
In practice, the logic shown in
As
In designing binary logic circuits according to the principles described herein, line segments having fixed gradients of low extended Hamming weights are constructed so as to approximate the function at hand. As many line segments are used as are required to meet the desired level of accuracy of the approximation. It is however advantageous to use a greater number of shorter line segments in regions where the gradient of the function changes quickly, than in regions where the gradient of the function changes slowly. This leads to an uneven distribution of break points. For instance, in the example shown in
As is known in the art, it is sometimes possible to implement hardware using a trinary or canonical bit representation of a binary number so as to provide a value having a lower Hamming weight for use in binary operations. For example, the binary number 0.1111, which has a Hamming weight of 4, can be represented in its canonical form as 1.000
Binary logic configured in accordance with the principles described herein can employ trinary or canonical bit representations in order to simplify a given hardware implementation. As appropriate, segment gradients can therefore be expressed in hardware in their canonical form. Where the canonical form of a segment gradient is used, the extended Hamming weight of the segment gradient is the Hamming weight of the segment gradient in its canonical form.
Note that binary logic configured in accordance with the principles set out herein makes use of fixed multiplication operations which can be efficiently implemented in hardware. No slope input is required to the multiplier arrays since each gradient multiplication factor is fixed by the architecture of each array. Furthermore, a lookup table is not required in order to calculate an approximation of a function. Binary logic configured in accordance with the principles described herein offers a high speed solution for approximating a function in hardware without consuming large areas of integrated circuit.
A process for designing a binary logic circuit (such as the circuit shown in
The selected number of linear segments having fixed gradients drawn from a set of gradient values having low extended Hamming weights are then fitted to the function at 403. One way of choosing appropriate gradients from a set of gradient values having low extended Hamming weights will now be described by way of example.
 1. Determine the value of the function at the break points and the endpoints of the defined range over which the function is to be approximated.
 2. Use the breakpoint and endpoint values to calculate the average gradient of the curve between adjacent end/break points (e.g. divide the difference between the values of the function at the adjacent end/break points by the difference between the corresponding x values).
 3. For each respective pair of adjacent end/break points, select for use as the gradient of the respective linear segment a gradient from a set of gradient values having low extended Hamming weights, the selected gradient being close to (and preferably as close as possible to) the calculated average gradient.
Once the gradients of the linear segments have been chosen, a base value for each segment can be determined 404—for example, a value at which that linear segment crosses an axis. This can be achieved by selecting one or more reference points with respect to which the linear segments are fixed in the function space. Typically these might be the start and/or end points of the function over the defined range. For instance, in
It will be appreciated that for each linear segment there is scope to choose a range of low extended Hamming weight gradient values and reference points with respect to which the segments are fixed. It can be advantageous to iterate steps 402404 in
This can help to deal with the case of monotonic increasing functions whose gradient reduces as x increases. For such functions, the choice of gradient determined according to the above example in which the start and end points lie on the function would typically mean that each linear segment largely lies slightly below the function. By performing an optimisation step so as to minimise the total mean squared error of the approximations over the defined range, a better fit can sometimes be determined—for example by choosing a slightly higher first slope, and slightly lower final slope so that each line segment has some sections that are below the curve, and others that are above. This can result in a lower mean squared error over the range.
The particular example shown in
Once the gradient and base value parameters of the linear segments of a given approximation to a function have been determined, a hardware representation of the approximation represented by the linear segments can be derived 405 using the lowest extended Hamming weight representation of the fixed gradient of each segment. Such a hardware representation could define a binary logic circuit according to the example shown in
A design process as set out in
A binary circuit derived in accordance with the above principles could be manufactured according to any suitable fabrication process. For example, an integrated circuit in the form of a silicon semiconductor device can be manufactured according to a conventional set of processing steps which might involve deposition on a silicon wafer, followed by patterning and packaging a die as an integrated circuit.
Note an adder refers to logic for both addition and subtraction. Since addition of a negative number is equivalent to subtraction, the terms add, adder and addition all refer broadly to either addition of a positive number or subtraction of a positive number, as well as addition of a negative number or subtraction of a negative number.
The binary logic circuit of
The terms software and computer readable program code as used herein includes executable code for processors (e.g. CPUs and/or GPUs), firmware, bytecode, programming language code such as C or OpenCL, and modules for reconfigurable logic devices such as FPGAs. Machinereadable code includes software and code for defining hardware representations of integrated circuits at any level, including at register transfer level (RTL), at highlevel circuit representations such as Verilog or VHDL, and lowerlevel representations such as OASIS and GDSII.
The algorithms and methods described herein could be performed by one or more physical processing units executing software that causes the unit(s) to perform the algorithms/methods. The or each physical processing unit could be any suitable processor, such as a CPU or GPU (or a core thereof), or fixed function or programmable hardware. The software could be stored in nontransitory form at a machine readable medium such as an integrated circuit memory, or optical or magnetic storage. A machine readable medium might comprise several memories, such as onchip memories, computer working memories, and nonvolatile storage devices.
The applicant hereby discloses in isolation each individual feature described herein and any combination of two or more such features, to the extent that such features or combinations are capable of being carried out based on the present specification as a whole in the light of the common general knowledge of a person skilled in the art, irrespective of whether such features or combinations of features solve any problems disclosed herein, and without limitation to the scope of the claims. The applicant indicates that aspects of the present invention may consist of any such individual feature or combination of features. In view of the foregoing description it will be evident to a person skilled in the art that various modifications may be made within the scope of the invention.