Non-volatile memory

• US 10,642,579 B2
• Filed: 05/25/2018
• Issued: 05/05/2020
• Est. Priority Date: 10/13/2017
• Status: Active Grant

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: Chen, Chih-Hsin, Wang, Shih-Chen
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US15/989,382
• Publication Number:
  US 20190115076A1
• Time in Patent Office: 711 Days
• Field of Search: 36518505, 365 63
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 7/1084 Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: H10B 41/10 characterised by the top-view layout

Abstract

A non-volatile memory includes a memory cell. A storage element of the memory cell has following structures. A first floating gate transistor includes a first floating gate, a first source/drain terminal and a second source/drain terminal. A second floating gate transistor includes the first floating gate, a third source/drain terminal and a fourth source/drain terminal. A third floating gate transistor includes a second floating gate, a fifth source/drain terminal and a sixth source/drain terminal. A fourth floating gate transistor includes the second floating gate, a seventh source/drain terminal and an eighth source/drain terminal. The first and third source/drain terminals are connected with a first terminal of the storage element. The second and fifth source/drain terminals are connected with each other. The fourth and seventh source/drain terminals are connected with each other. The sixth and eighth source/drain terminals are connected with a second terminal of the storage element.

Claims

1. A non-volatile memory comprising a memory cell, the memory cell comprising a storage element, the storage element comprising:

a first floating gate transistor comprising a first floating gate, a first source/drain terminal and a second source/drain terminal;

a second floating gate transistor comprising the first floating gate, a third source/drain terminal and a fourth source/drain terminal;

a third floating gate transistor comprising a second floating gate, a fifth source/drain terminal and a sixth source/drain terminal; and

a fourth floating gate transistor comprising the second floating gate, a seventh source/drain terminal and an eighth source/drain terminal,

wherein the second source/drain terminal is connected with the fifth source/drain terminal, and the fourth source/drain terminal is connected with the seventh source/drain terminal;

wherein the first floating gate transistor has a first channel length, the second floating gate transistor has a second channel length, the third floating gate transistor has a third channel length, and the fourth floating gate transistor has a fourth channel length, wherein the first channel length is larger than the third channel length, and the fourth channel length is larger than the second channel length.

2. A non-volatile memory comprising a memory cell, the memory cell comprising a storage element, the storage element comprising:

a first floating gate transistor comprising a first floating gate, a first source/drain terminal and a second source/drain terminal;

a second floating gate transistor comprising the first floating gate, a third source/drain terminal and a fourth source/drain terminal;

a third floating gate transistor comprising a second floating gate, a fifth source/drain terminal and a sixth source/drain terminal; and

a fourth floating gate transistor comprising the second floating gate, a seventh source/drain terminal and an eighth source/drain terminal,

wherein the second source/drain terminal is connected with the fifth source/drain terminal, and the fourth source/drain terminal is connected with the seventh source/drain terminal;

wherein the memory cell further comprises;

a control transistor comprising a first gate, a ninth source/drain terminal and a tenth source/drain terminal, wherein the first gate is connected with a word line, the ninth source/drain terminal is connected with a bit line, and the tenth source/drain terminal is connected with the sixth source/drain terminal and the eighth source/drain terminal.

3. A non-volatile memory comprising a memory cell, the memory cell comprising a storage element, the storage element comprising:

a first floating gate transistor comprising a first floating gate, a first source/drain terminal and a second source/drain terminal;

a second floating gate transistor comprising the first floating gate, a third source/drain terminal and a fourth source/drain terminal;

a third floating gate transistor comprising a second floating gate, a fifth source/drain terminal and a sixth source/drain terminal; and

a fourth floating gate transistor comprising the second floating gate, a seventh source/drain terminal and an eighth source/drain terminal,

wherein the second source/drain terminal is connected with the fifth source/drain terminal, and the fourth source/drain terminal is connected with the seventh source/drain terminal;

wherein the memory cell further comprises;

a select transistor comprising a first gate, a ninth source/drain terminal and a tenth source/drain terminal, wherein the first gate is connected with a select line, the ninth source/drain terminal is connected with a source line, and the tenth source/drain terminal is connected with the first source/drain terminal and the third source/drain terminal.

4. The non-volatile memory as claimed in claim 3, wherein the memory cell further comprises a first capacitor and a second capacitor, the first capacitor is connected between the first floating gate and a control line, and the second capacitor is connected between the second floating gate and the control line.

5. A non-volatile memory comprising a memory cell, the memory cell comprising a storage element, the storage element comprising:

a first floating gate transistor comprising a first floating gate, a first source/drain terminal and a second source/drain terminal;

a second floating gate transistor comprising the first floating gate, a third source/drain terminal and a fourth source/drain terminal;

a third floating gate transistor comprising a second floating gate, a fifth source/drain terminal and a sixth source/drain terminal; and

a fourth floating gate transistor comprising the second floating gate, a seventh source/drain terminal and an eighth source/drain terminal,

wherein the second source/drain terminal is connected with the fifth source/drain terminal, and the fourth source/drain terminal is connected with the seventh source/drain terminal;

wherein the memory cell further comprises a first capacitor and a second capacitor, the first capacitor is connected between the first floating gate and an erase line, and the second capacitor is connected between the second floating gate and the erase line.