Technologies for indirectly calling vector functions

• US 10,642,587 B2
• Filed: 03/11/2016
• Issued: 05/05/2020
• Est. Priority Date: 03/11/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ido, Hideki Saito, Preis, Serge V., Kozhukhov, Sergey S., Tian, Xinmin, Maslov, Sergey V., Nelson, Clark, Yu, Jianfei
• Primary Examiner(s): Kendall, Chuck O
• Application Number:
  US16/076,735
• Publication Number:
  US 20190050212A1
• Time in Patent Office: 1,516 Days
• Field of Search: 717117
• CPC Class Codes: G06F 8/4441 Reducing the execution time required by the program code
• CPC Class Codes: G06F 8/445 Exploiting fine grain parallelism, i.e. parallelism at instruction level run-time instruction scheduling G06F9/3836

Abstract

Technologies for indirectly calling vector functions include a compute device that includes a memory device to store source code and a compiler module. The compiler module is to identify a set of declarations of vector variants for scalar functions in the source code, generate a vector variant address map for each set of vector variants, generate an offset map for each scalar function, and identify, in the source code, an indirect call to the scalar functions, wherein the indirect call is to be vectorized. The compiler module is also to determine, based on a context of the indirect call, a vector variant to be called and store, in object code and in association with the indirect call, an offset into one of the vector variant address maps based on (i) the determined vector variant to be called and (ii) the offset map that corresponds to each scalar function.

Claims

1. A compute device for indirectly calling vector functions, the compute device comprising:

a memory device to store source code;

a compiler module to;

identify, in the source code, declarations of scalar functions;

identify, in the source code, a set of declarations of vector variants for each of the scalar functions;

generate a vector variant address map for each set of vector variants, wherein each vector variant address map includes addresses of the vector variants of the associated scalar function;

generate an offset map for each scalar function, wherein each offset map includes offsets into the associated vector variant address map and each offset is to a different one of the vector variant addresses;

identify, in the source code, an indirect call to the scalar functions, wherein the indirect call is to be vectorized;

determine, based on a context of the indirect call, a vector variant to be called; and

store, in object code and in association with the indirect call, an offset into one of the vector variant address maps based on (i) the determined vector variant to be called and (ii) the offset map that corresponds to each scalar function.

2. The compute device of claim 1, wherein to generate the vector variant address map comprises to additionally include an address of the associated scalar function in the vector variant address map.

3. The compute device of claim 1, wherein to generate the vector variant address map comprises to order the addresses in the vector variant address map based on a predefined layout rule.

4. The compute device of claim 1, wherein to generate the vector variant address map comprises to order the addresses in the vector variant address map based on an alphabetical order of names of the vector variants.

5. The compute device of claim 1, wherein to determine the vector variant to be called comprises to determine the vector variant to be called based on a length of the vector.

6. The compute device of claim 1, wherein to determine the vector variant to be called comprises to determine the vector variant to be called based on a target architecture for the object code.

7. The compute device of claim 1, wherein to determine the vector variant to be called comprises to determine the vector variant based on a value progression pattern.

8. The compute device of claim 1, wherein the compiler module is further to store the vector variant address maps in the object code.

9. The compute device of claim 1, further comprising an execution module to:

read the object code generated from the source code;

identify, in the object code, the indirect call to be vectorized;

determine an address of each associated vector variant, based on (i) the offset stored in association with the indirect call and (ii) the vector variant address map for each vector variant; and

execute the vector variants based on the determined addresses.

10. One or more non-transitory, computer-readable storage media comprising a plurality of instructions that, when executed, cause a compute device to:

identify declarations of scalar functions in a source code stored in a memory device of the compute device;

identify a set of declarations of vector variants for each of the scalar functions in the source code;

generate a vector variant address map for each set of vector variants, wherein each vector variant address map includes addresses of the vector variants of the associated scalar function;

generate an offset map for each scalar function, wherein each offset map includes offsets into the associated vector variant address map and each offset is to a different one of the vector variant addresses;

identify in the source code, an indirect call to the scalar functions, wherein the indirect call is to be vectorized;

determine, based on a context of the indirect call, a vector variant to be called; and

store, in object code and in association with the indirect call, an offset into one of the vector variant address maps based on (i) the determined vector variant to be called and (ii) the offset map that corresponds to each scalar function.

11. The one or more non-transitory, computer-readable storage media of claim 10, wherein to generate the vector variant address map comprises to include an address of the associated scalar function in the vector variant address map.

12. The one or more non-transitory, computer-readable storage media of claim 10, wherein to generate the vector variant address map comprises to order the addresses in the vector variant address map based on a predefined layout rule.

13. The one or more non-transitory, computer-readable storage media of claim 10, wherein to generate the vector variant address map comprises to order the addresses in the vector variant address map based on an alphabetical order of names of the vector variants.

14. The one or more non-transitory, computer-readable storage media of claim 10, wherein to determine the vector variant to be called comprises to determine the vector variant to be called based on a length of the vector.

15. The one or more non-transitory, computer-readable storage media of claim 10, wherein to determine the vector variant to be called comprises to determine the vector variant to be called based on a target architecture for the object code.

16. The one or more non-transitory, computer-readable storage media of claim 10, wherein to determining the vector variant to be called comprises to determine the vector variant based on a value progression pattern.

17. The one or more non-transitory, computer-readable storage media of claim 10, further comprising instructions that, when executed, cause the compute device to store the vector variant address maps in the object code.

18. A method for indirectly calling vector functions, the method comprising:

identifying, by a compute device, declarations of scalar functions in a source code stored in a memory device of the compute device;

identifying, by the compute device, a set of declarations of vector variants for each of the scalar functions in the source code;

generating, by the compute device, a vector variant address map for each set of vector variants, wherein each vector variant address map includes addresses of the vector variants of the associated scalar function;

generating, by the compute device, an offset map for each scalar function, wherein each offset map includes offsets into the associated vector variant address map and each offset is to a different one of the vector variant addresses;

identifying, by the compute device, in the source code, an indirect call to the scalar functions, wherein the indirect call is to be vectorized;

determining, by the compute device, based on a context of the indirect call, a vector variant to be called; and

storing, by the compute device, in object code and in association with the indirect call, an offset into one of the vector variant address maps based on (i) the determined vector variant to be called and (ii) the offset map that corresponds to each scalar function.

19. The method of claim 18, wherein generating the vector variant address map comprises including an address of the associated scalar function in the vector variant address map.

20. The method of claim 18, wherein generating the vector variant address map comprises ordering the addresses in the vector variant address map based on a predefined layout rule.

21. The method of claim 18, wherein generating the vector variant address map comprises ordering the addresses in the vector variant address map based on an alphabetical order of names of the vector variants.

22. The method of claim 18, wherein determining the vector variant to be called comprises determining the vector variant to be called based on a length of the vector.

23. The method of claim 18, wherein determining the vector variant to be called comprises determining the vector variant to be called based on a target architecture for the object code.

24. The method of claim 18, wherein determining the vector variant to be called comprises determining the vector variant based on a value progression pattern.

25. The method of claim 18, further comprising storing, by the compute device, the vector variant address maps in the object code.