Method and system for converting a single-threaded software program into an application-specific supercomputer

• US 10,642,588 B2
• Filed: 10/22/2018
• Issued: 05/05/2020
• Est. Priority Date: 11/15/2011
• Status: Active Grant

• Current Assignee: Global Supercomputing Corporation
• Original Assignee: Global Supercomputing Corporation
• Inventors: Ebcioglu, Kemal, Kultursay, Emre
• Primary Examiner(s): Chen, Qing
• Application Number:
  US16/166,164
• Publication Number:
  US 20190114158A1
• Time in Patent Office: 561 Days
• Field of Search: 717136-161, 716105, 716116, 716117, 716124, 716125, 716128, 716131
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/0895 of parts of caches, e.g. directory or tag array
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus
• CPC Class Codes: G06F 2115/10 Processors
• CPC Class Codes: G06F 2212/455 Image or video data
• CPC Class Codes: G06F 2212/6026 Prefetching based on access pattern detection, e.g. stride based prefetch
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/323 Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 8/40 Transformation of program code
• CPC Class Codes: G06F 8/4452 Software pipelining
• CPC Class Codes: G06F 8/452 Loops
• CPC Class Codes: G06F 9/52 Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention comprises (i) a compilation method for automatically converting a single-threaded software program into an application-specific supercomputer, and (ii) the supercomputer system structure generated as a result of applying this method. The compilation method comprises: (a) Converting an arbitrary code fragment from the application into customized hardware whose execution is functionally equivalent to the software execution of the code fragment; and (b) Generating interfaces on the hardware and software parts of the application, which (i) Perform a software-to-hardware program state transfer at the entries of the code fragment; (ii) Perform a hardware-to-software program state transfer at the exits of the code fragment; and (iii) Maintain memory coherence between the software and hardware memories. If the resulting hardware design is large, it is divided into partitions such that each partition can fit into a single chip. Then, a single union chip is created which can realize any of the partitions.

Claims

1. A directory-mapped coherent cache memory hierarchy with a write-update protocol of a partitioned application-specific supercomputer comprising a memory including a plurality of ports and a cache, where:

a. whenever a store instruction is executed to a shared line in the cache, all copies of the shared line in other caches are automatically updated with the same store instruction;

b. the automatic update is accomplished with message communication, over a plurality of scalable networks, only among caches having the shared line, and a directory unit responsible for the shared line in the caches, therefore reducing communication overhead; and

c. a compiler guarantees, by introducing synchronization actions, that any two load/store instructions, one of which is a store instruction, which can simultaneously arrive at a cache line, are independent, therefore allowing re-ordering of load/store instructions in the plurality of scalable networks, and simplifying cache hardware;

where the compiler automatically translates a single-threaded software program code fragment into the partitioned application-specific supercomputer functionally equivalent to the single-threaded software program code fragment, in part by creating one or more customized coherent cache memory hierarchies with the write-update protocol, and where each among the one or more customized coherent cache memory hierarchies with the write-update protocol has a minimum number of ports and data width per port for reducing memory area and power consumption.

2. The directory-mapped coherent cache memory hierarchy with the write-update protocol of the partitioned application-specific supercomputer of claim 1, further comprising:

a set of line states comprising an exclusive state, a shared state, an invalid state, but not including a modified state.