Embedded device and program updating method

• US 10,642,596 B2
• Filed: 02/28/2017
• Issued: 05/05/2020
• Est. Priority Date: 03/01/2016
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Tanimoto, Tadaaki, Hagiwara, Kesami, Morita, Naoyuki
• Primary Examiner(s): Bullock, Jr., Lewis A
• Assistant Examiner(s): Huynh, Tina
• Application Number:
  US15/445,510
• Publication Number:
  US 20170255459A1
• Time in Patent Office: 1,162 Days
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 2212/251 Local memory within processor subsystem
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 8/65 Updates security arrangements therefor G06F21/57
• CPC Class Codes: G06F 8/654 using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
• CPC Class Codes: G06F 8/658 Incremental updates; Differential updates
• CPC Class Codes: G06F 9/44521 Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading
• CPC Class Codes: H04L 67/34 involving the movement of software or configuration parameters network booting or remote initial program loading [RIPL] G06F9/4416

Abstract

An object of the present invention is to perform a program updating process without reconstructing a program using a pre-update program and an update differential program. An embedded device has a nonvolatile memory having a plurality of planes from/to which data can be read/written independently and an address translator performing address translation by using an address translation table. When an address obtained by decoding an instruction by a CPU is an address corresponding to a change part in a default program, the address translator translates the address to an address in which a differential program is disposed.

Claims

1. An embedded device comprising:

a network input unit receiving update information via a network;

a first nonvolatile memory having a plurality of planes each of which can be accessed independently;

a second nonvolatile memory having a plurality of planes each of which is accessible independently;

a CPU executing a program disposed in the first nonvolatile memory;

a bus disposed between the CPU and the first nonvolatile memory;

a first address translator performing address translation for a program by using an address translation table included in update information received by the network input unit; and

a second address translator performing address translation for data to be used by a program by using an address translation table included in update information received by the network input unit,

wherein the CPU executes a program disposed in the first nonvolatile memory by using data disposed in the second nonvolatile memory,

wherein the first address translator is disposed between the CPU and the bus,

wherein in the first nonvolatile memory, a default program is disposed in a first plane and a differential program with respect to the default program, included in update information received by the network input is disposed in a second plane,

wherein in the second nonvolatile memory, default data is disposed in a first plane and differential data with respect to the default data, included in update information received by the network input unit is disposed in a second plane,

wherein when an address to be obtained by the CPU is an address corresponding to a change part in the default program, the first address translator translates the address to an address in which the differential program is disposed and outputs the translated address to the bus,

wherein when an address obtained by decoding an instruction by the CPU is an address corresponding to a change part in the default data, the second address translator translates the address to an address in which the differential data is disposed,

wherein the CPU executes the differential program in accordance with the address translated by the first address translator, and

wherein the CPU executes a process using the differential data in accordance with the address translated by the second address translator.

2. The embedded device according to claim 1,

wherein the number of planes of the first nonvolatile memory is three.

3. The embedded device according to claim 1,

wherein the first address translator changes an upper bit sequence of predetermined number of bits in an address obtained by decoding an instruction by the CPU and couples the changed upper bit sequence and a lower bit sequence of the address, thereby translating the address to an address in which the differential program is disposed.

4. The embedded device according to claim 3,

wherein when size of a differential code which replaces a code of a part to be substituted in the default program is larger than that of a code of the part to be substituted, or when the size of the code to be substituted or the size of the differential code is larger than segment size as size of a memory region corresponding to the predetermined number of bits, the first address translator translates a start address of the code of the part to be substituted to a predetermined address, and

wherein the predetermined address is an address in which an instruction related to a jump instruction to a start address of an instruction sequence which replaces the code of the part to be substituted is stored.

5. The embedded device according to claim 1,

wherein the network input unit receives the update information including information constructing a program restoration point in addition to the differential program.

6. The embedded device according to claim 1, further comprising a signature verifying unit verifying signature of the update information,

wherein when validity is confirmed by the signature verifying unit, the CPU executes the differential program.

7. The embedded device according to claim 1,

wherein the second nonvolatile memory stores management information managing a write destination address when information included in the update information is written in the first nonvolatile memory or the second nonvolatile memory and erasure block number corresponding to the address, and

wherein at the time of erasing information stored in the first nonvolatile memory or the second nonvolatile memory, a region designated by the erasure block number indicated in the management information is erased.

8. The embedded device according to claim 6, further comprising a control circuit which allows writing to the first nonvolatile memory of the update information when the update information is confirmed to be valid by the signature verifying unit.

9. The embedded device according to claim 1,

wherein the network input unit receives update information excluding a part overlapped with update information already disposed in the first nonvolatile memory, and

wherein the differential program obtained by eliminating the overlapped part is newly disposed in addition to the overlapped part already disposed in the first nonvolatile memory.

10. The embedded device according to claim 1,

wherein the second nonvolatile memory stores management information managing a write destination address when information included in the update information is written in the first nonvolatile memory or the second nonvolatile memory and erasure block number corresponding to the address, and

wherein when power supply stops at the time of writing the update information to the first nonvolatile memory or the second nonvolatile memory or at the time of operation of applying the update information, after the power supply recovers, when the management information can be referred to, the update information written before the stop of the power supply is erased according to the management information.

11. The embedded device according to claim 1,

wherein the first address translator translates an address of an instruction, and

wherein the second address translator translates an address of an operand.