Apparatus and methods for in-application programming of flash-based programmable logic devices

• US 10,642,601 B2
• Filed: 02/14/2017
• Issued: 05/05/2020
• Est. Priority Date: 02/28/2011
• Status: Active Grant

• Current Assignee: Microsemi SoC Corp. (Microchip Technology Incorporated)
• Original Assignee: Microsemi SoC Corp. (Microchip Technology Incorporated)
• Inventors: Narayanan, Venkatesh, Irving, Kenneth R., Kiu, Ming-Hoe
• Primary Examiner(s): Giroux, George
• Application Number:
  US15/432,659
• Publication Number:
  US 20170161224A1
• Time in Patent Office: 1,176 Days
• Field of Search: None
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 15/7871 Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
• CPC Class Codes: G06F 15/7882 for self reconfiguration
• CPC Class Codes: G06F 8/654 using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

An architecture disposed in an integrated circuit for in-application programming of flash-based programmable logic devices includes a processor coupled to a processor system bus. An I/O peripheral is coupled to the processor over the system bus and is also coupled to an off-chip data source. A programmable logic device fabric includes flash-based programmable devices. A program controller is coupled to the flash-based programmable devices. An in-application programming controller is coupled to the program controller and is coupled to the processor over the system bus.

Claims

1. An architecture disposed in an integrated circuit for in-application programming of flash-based programmable logic devices comprising:

a processor in the integrated circuit and coupled to a processor system bus;

an I/O peripheral in the integrated circuit and coupled to the processor over the system bus and coupled to an off-chip data source;

a programmable logic array fabric in the integrated circuit and including flash-based programmable devices;

a programming controller in the integrated circuit configured to program the flash-based programmable devices; and

an in-application programming controller in the integrated circuit and coupled to the processor, the in-application programming controller separate from the programming controller and configured to control the operation of the programming controller in response to commands from the processor;

wherein the processor is configured to perform other tasks while the in-application programming controller executes the commands.

2. The architecture of claim 1 wherein the in-application programming controller is coupled to the processor over the system bus.

3. The architecture of claim 1 wherein the in-application programming controller is coupled to the processor over a JTAG interface.

4. The architecture of claim 1 wherein the in-application programming controller is configured as a state machine.

5. The architecture of claim 1 wherein the in-application programming controller is configured as a FIFO coupled between the system bus and the programming controller.

6. The architecture of claim 1 wherein the in-application programming controller communicates an interrupt to the processor.

7. The architecture of claim 1 wherein the programming controller is coupled to non-volatile memory elements associated with the programmable logic array fabric in the integrated circuit.

8. The architecture of claim 1 wherein the programming controller is coupled to non-volatile memory elements associated with user memory in the integrated circuit.

9. The architecture of claim 1 wherein the in-application program controller is configured to program nonvolatile memory by rows.

10. The architecture of claim 1 wherein the in-application program controller is configured to program nonvolatile memory by segments.