Memory device performing parallel arithmetic processing and memory module including the same
First Claim
Patent Images
1. A memory module comprising:
- a first memory device configured to receive data and first information from a hardware accelerator, to generate an arithmetic result by performing arithmetic processing using the data and the first information, and to output the arithmetic result through an interface that communicates with at least one other memory device; and
a second memory device configured to receive the arithmetic result from the first memory device through the interface without using the hardware accelerator, and to store the arithmetic result,wherein;
the first memory device comprises a first die configured to communicate with a device outside the first memory device, and a plurality of second dies,each of the second dies comprises a memory cell array and an arithmetic circuit configured to perform the arithmetic processing, andthe first die comprises a first interface circuit configured to exchange the data with the hardware accelerator and a second interface circuit configured to exchange the arithmetic result with the second memory device.
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Abstract
A memory module includes a first memory device configured to receive data and first information from a hardware accelerator, to generate an arithmetic result by performing arithmetic processing using the data and the first information, and to output the arithmetic result through an interface with at least one other memory device; and a second memory device configured to receive the arithmetic result from the first memory device through the interface without using the hardware accelerator, and to store the arithmetic result.
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Citations
19 Claims
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1. A memory module comprising:
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a first memory device configured to receive data and first information from a hardware accelerator, to generate an arithmetic result by performing arithmetic processing using the data and the first information, and to output the arithmetic result through an interface that communicates with at least one other memory device; and a second memory device configured to receive the arithmetic result from the first memory device through the interface without using the hardware accelerator, and to store the arithmetic result, wherein; the first memory device comprises a first die configured to communicate with a device outside the first memory device, and a plurality of second dies, each of the second dies comprises a memory cell array and an arithmetic circuit configured to perform the arithmetic processing, and the first die comprises a first interface circuit configured to exchange the data with the hardware accelerator and a second interface circuit configured to exchange the arithmetic result with the second memory device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A memory module comprising:
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an interposer having wiring for signal transmission formed thereon; and a plurality of high bandwidth memories (HBMs) mounted on the interposer, wherein each of the HBMs comprises a plurality of core dies, and a buffer die configured to communicate with a device outside each HBM, each of the core dies comprising a memory cell array and an arithmetic circuit configured to perform arithmetic processing, a first HBM among the plurality of HBMs is configured to receive data from a memory controller through a buffer die and perform arithmetic processing using the data in a plurality of core dies in parallel, and the memory module is configured such that an arithmetic result of the first HBM is provided to a second HBM among the plurality of HBMs through data communication between the buffer die of the first HBM and a buffer die of the second HBM. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A memory device comprising:
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a first die configured to interface with an external memory controller and an external memory device; a plurality of second dies stacked on the first die, each of the second dies comprising a memory cell array; and a through-silicon via (TSV) region configured to transmit and receive a signal between the first die and the plurality of second dies, wherein each of the second dies comprises a plurality of channels, each of the channels comprising an arithmetic circuit configured to perform arithmetic processing using data provided from the external memory controller, and the first die comprises; a first interface circuit configured to receive the data and an arithmetic command by communicating with the external memory controller and to transmit the received data to the second dies through the TSV region; and a second interface circuit configured to receive an arithmetic result from the second dies through the TSV region and to output the arithmetic result by communicating with the external memory device. - View Dependent Claims (18, 19)
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Specification