Arithmetic processing device and control method of the arithmetic processing device

• US 10,642,622 B2
• Filed: 10/13/2017
• Issued: 05/05/2020
• Est. Priority Date: 12/27/2016
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Kuramoto, Masahiro
• Primary Examiner(s): Sandifer, Matthew D
• Application Number:
  US15/782,881
• Publication Number:
  US 20180181406A1
• Time in Patent Office: 935 Days
• CPC Class Codes: G06F 15/8015 One dimensional arrays, e.g. rings, linear arrays, buses
• CPC Class Codes: G06F 17/15 Correlation function computation including computation of convolution operations arithmetic circuits for sum of products per se, e.g. multiply-accumulators G06F7/5443; digital filters, e.g. FIR, IIR, adaptive filters H03H17/00
• CPC Class Codes: G06F 17/16 Matrix or vector computation , e.g. matrix-matrix or matrix-vector multiplication, matrix factorization matrix transposition G06F7/78
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/3895 for complex operations, e.g. multidimensional or interleaved address generators, macros
• CPC Class Codes: G06N 3/04 Architecture, e.g. interconnection topology
• CPC Class Codes: G06N 3/06 Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G06N 3/084 Backpropagation, e.g. using gradient descent

Abstract

Each of product-sum arithmetic units 501 to 503 acquires, from a register file 410, different pieces of first element data included in a first predetermined row of first data that forms a matrix; acquires, from a register file 420, same pieces of second element data included in a second predetermined row of second data that forms a matrix; performs a row portion operation that is an operation performed on the first data by an amount corresponding to a single row by performing a process of performing an operation using the acquired first element data and the second element data; and performs an operation by using the first data and the second data based on the result of the row portion operation.

Claims

1. An arithmetic processing device comprising:

a memory, a plurality of first register files, a plurality of second register files, and a plurality of arithmetic units, wherein each arithmetic unit has a plurality of product sum arithmetic circuits, and each product sum arithmetic circuit has an adder and a multiplier;

the memory stores first data which has pieces of element data included in a first matrix and second data which has pieces of element data included in a second matrix;

a first register file of the plurality of first register files is arranged for each of the arithmetic units and stores a first respective predetermined row of the first data that is stored in the memory, a second register file of the plurality of second register files is arranged for each of the arithmetic units and stores a second predetermined row of the second data that is stored in the memory;

a pointer control circuit sets a position of a pointer that designates data that is stored in the first register files and the second register files;

and each product-sum arithmetic circuit

performs a first operation which includes first acquiring different pieces of first element data that is designated by the pointer whose position is set by the pointer control circuit from a top row location of its first respective predetermined row, second acquiring same pieces of second element data that is designated by the pointer whose position is set by the pointer control circuit from a top row location of the second predetermined row, and performing a first multiply operation by using the first acquired first element data and the second acquired second element data, and performing a first add operation based on a result of the first multiply operation and a result of the previous first multiply operation,

performs a second operation which includes repeat acquiring different pieces of first element data which is next sequential different data that is designated by the pointer that is moved by one from the first acquiring by the pointer control circuit in a row direction of its first respective predetermined row, repeat acquiring same pieces of second element data which is next sequential different data that is designated by the pointer that is moved by one from the first acquiring by the pointer control circuit in a row direction of the second predetermined row, performing a repeat multiply operation by using the repeat acquired first element data and the repeat acquired second element data, and performing a repeat add operation based on a result of the repeat multiply operation and a result of the previous repeat multiply operation,

and repeats the second operation for each of the first element data in its first respective predetermined row of the first matrix and each of the second element data in the second predetermined row of the second matrix.

2. The arithmetic processing device according to claim 1, wherein each of the plurality of arithmetic units determines, based on the size of the first data or the second data, the number of the arithmetic units that are used to perform the operation and determines the number of second arithmetic units included in the arithmetic units based on the size of one of the first data and the second data and based on an amount of movement of the second data.

3. The arithmetic processing device according to claim 1, each of the product-sum arithmetic circuit acquires the first element data that is moved forward by an amount corresponding to the number of strides for each operation starting from the first element data, as the top position, having a number incremented by 1 from the top in the first predetermined row, sequentially acquires, in numerical order for each operation, the second element data arrayed with consecutive numbers included in the second predetermined row, and performs the row portion operation by repeating an operation of adding a value obtained by multiplying the acquired first element data by the second element data to the last operation result.

4. The arithmetic processing device according to claim 1, wherein each of the product-sum arithmetic circuit acquires, from among the pieces of the first element data arrayed with consecutive numbers included in the first predetermined row, the different pieces of the first element data in numerical order, acquires, for each operation in numerical order, the second element data arrayed with consecutive numbers included in the second predetermined row, and performs the row portion operation by repeating an operation of adding a value obtained by multiplying the acquired first element data by the second element data to the operation result that is calculated in the last operation by the product-sum arithmetic circuit located at the position ahead by an amount corresponding to the number of strides.

5. A control method of an arithmetic processing device connected to a memory that stores first data which has pieces of element data included in a first matrix and second data which has pieces of element data that form a second matrix, the control method comprising:

storing, in each of a plurality of first register files arranged for each of a plurality of computing units, a first respective predetermined row of the first data stored in the memory, wherein each computing unit has a plurality of product-sum computing circuits;

storing, in each of a plurality of second register files arranged for each of the plurality of computing units, a second predetermined row of the second data stored in the memory;

setting, by a pointer control circuit, a position of a pointer that designates data that is stored in the first register file and the second register file;

causing each of the product-sum computing circuits to perform a first operation which includes first acquiring different pieces of first element data that is designated by the pointer whose position is set by the pointer control circuit from a top row location of its first respective predetermined row, second acquiring same pieces of second element data that is designated by the pointer whose position is set by the pointer control circuit from a top row location of the second predetermined row, and performing a first multiply operation by using the first acquired first element data and the second acquired second element data, and performing a first add operation based on a result of the first multiply operation and a result of the previous first multiply operation,

causing each of the product-sum computing circuits to perform a second operation which includes repeat acquiring different pieces of first element data which is next sequential different data designated by the pointer that is moved by one from the first acquiring in a row direction of its first respective predetermined row, repeat acquiring same pieces of second element data which is next sequential different data that is designated by the pointer that is moved by one from the first acquiring in a row direction of the second predetermined row, performing a repeat multiply operation by using the repeat acquired first element data and the repeat acquired second element data, and performing a repeat add operation based on a result of the repeat multiply operation and a result of the previous repeat multiply operation;

and causing each of the product-sum computing circuits to perform repeating the second operation for each of the first element data in its first respective predetermined row of the first matrix and each of the second element data in the second predetermined row of the second matrix.