Memory management method and apparatus

• US 10,642,644 B2
• Filed: 06/27/2016
• Issued: 05/05/2020
• Est. Priority Date: 06/27/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Wu, Keqiang, Lu, Jiwei, Yamada, Koichi, Lee, Yong-Fong
• Primary Examiner(s): Simonetti, Nicholas J
• Application Number:
  US15/193,562
• Publication Number:
  US 20170371578A1
• Time in Patent Office: 1,408 Days
• CPC Class Codes: G06F 9/467 Transactional memory G06F9/528 takes precedence
• CPC Class Codes: G06F 9/528 by using speculative mechanisms

Abstract

Methods, apparatus, and system to identify a memory contention with respect to a process, re-write the process to form a transactional process, and execute the transactional process in a speculative execution.

Claims

1. An apparatus for computing, comprising:

a computer processor and a memory; and

a transactional translation module operated by the computer processor to manage a memory utilization with respect to a process of the apparatus, wherein to manage the memory utilization with respect to the process, the transactional translation module is to identify a memory contention with respect to the process, re-write the process to form a transactional process, and execute the transactional process in a speculative execution.

2. The apparatus according to claim 1, further comprising a process analysis module operated by the computer processor to identify the memory contention with respect to the process, wherein to identify the memory contention with respect to the process, the process analysis module is to obtain a performance data with respect to the process and determine if the performance data is consistent with the memory contention.

3. The apparatus according to claim 2, wherein the process analysis module is to determine if the performance data is consistent with the memory contention according to whether the process exceeds a central processing unit process utilization threshold for the computer processor.

4. The apparatus according to claim 3, wherein the process analysis module is to determine if the performance data is consistent with the memory contention further according to at least one of a determination that the process comprises a loop body with assembly or machine instructions greater than an assembly or machine instruction threshold or a determination that the process comprises an atomic instruction or an atomic group of instructions and wherein the transactional translation module is to identify the memory contention with respect to the process by determining if a core of the processor exceeds a processor utilization threshold when the process is executed by the core.

5. The apparatus according to claim 1, wherein the transactional translation module is to determine whether the transactional process may be executed by a hardware-based transactional execution process, wherein the hardware-based transactional execution process comprises a lock elision, wherein the lock elision comprises at least one of a hardware lock elision or a restricted transactional memory.

6. The apparatus according to claim 1, wherein to re-write the process to form the transactional process comprises to decode a critical code region of the process, to identify regular lock/unlock instructions in the critical code region, to determine a code representation of the critical code region, wherein the code representation of the critical code region comprises a transactional lock acquire and a transactional lock release, to determine a binary machine code corresponding to the code representation of the critical code region as the transactional process, and to store the transactional process in at least one of a register or a stack of the computer processor for execution, wherein the speculative execution results in one of an atomic commit with respect to the transactional process or ignoring the result of the transactional process.

7. A computer implemented method, comprising:

identifying, by a computer processor, a memory contention with respect to a process of the computer processor;

re-writing, by the computer processor, the process to form a transactional process; and

executing, by the computer processor, the transactional process in a speculative execution.

8. The method according to claim 7, wherein identifying a memory contention with respect to the process further comprises obtaining a performance data with respect to the process and determining if the performance data is consistent with the memory contention, wherein determining if the performance data is consistent with the memory contention comprises determining if a central processing unit process utilization threshold is exceeded when the process is executed.

9. The method according to claim 8, wherein determining if the performance data is consistent with the memory contention further comprises at least one of determining that the process comprises a loop body with assembly or machine instructions greater than an assembly instruction threshold or determining that the process comprises an atomic instruction or an atomic group of instructions.

10. The method according to claim 7, further comprising determining, by the computer processor, whether the transactional process may be executed by a hardware-based transactional execution process, wherein the hardware-based transactional execution process comprises a lock elision, wherein the lock elision comprises at least one of a hardware lock elision or a restricted transactional memory.

11. The method according to claim 7, wherein re-writing the process to form the transactional process comprises decoding a critical code region of the process, identifying regular lock/unlock instructions in the critical code region, determining a code representation of the critical code region, wherein the code representation of the critical code region comprises a transactional lock acquire and a transactional lock release, determining a binary machine code corresponding to the code representation of the critical code region as the transactional process, and storing the transactional process in at least one of a register or a stack of the computer processor for execution, wherein the speculative execution results in one of an atomic commit with respect to the transactional process or ignoring the result of the transactional process.

12. An apparatus for computing, comprising:

one or more processors;

program means operated by the one or more processors to identify a memory contention with the apparatus with respect to a process of the apparatus including program means to obtain a performance data with respect to the process and program means to determine if the performance data is consistent with the memory contention;

program means operated by the one or more processors to re-write the process to form a transactional process of the apparatus; and

program means operated by the one or more processors to execute the transactional process in a speculative execution of the apparatus.

13. The apparatus according to claim 12, wherein program means to determine if the performance data is consistent with the memory contention comprises program means operated by the one or more processors to determine if a central processing unit process utilization threshold for the apparatus is exceeded when the process is executed and program means operated by the one or more processors to determine at least one of whether the process comprises a loop body with assembly or machine instructions greater than an assembly or machine instruction threshold or whether the process comprises an atomic instruction or an atomic group of instructions.

14. The apparatus according to claim 12, further comprising program means operated by the one or more processors to determine whether the transactional process may be executed by a hardware-based transactional execution process, wherein the hardware-based transactional execution process comprises a lock elision, and wherein the lock elision comprises at least one of a hardware lock elision or a restricted transactional memory.

15. The apparatus according to claim 12, wherein program means to re-write the process to form the transactional process comprises program means operated by the one or more processors to decode a critical code region of the process, identify regular lock/unlock instructions in the critical code region, determine a code representation of the critical code region, wherein the code representation of the critical code region comprises a transactional lock acquire and a transactional lock release, determine a binary machine code corresponding to the code representation of the critical code region as the transactional process, and program means operated by the one or more processors to store the transactional process in at least one of a register or a stack of the apparatus for execution and wherein the speculative execution results in one of an atomic commit with respect to the transactional process or ignoring the result of the transactional process.

16. One or more non-transitory computer-readable media comprising instructions that cause a computer device, in response to execution of the instructions by a processor of the computer device, to:

identify a memory contention with respect to a process of the computer device;

re-write the process to form a transactional process of the computer device; and

execute the transactional process in a speculative execution by the computer device.

17. The non-transitory computer-readable media according to claim 16, wherein to identify the memory contention with respect to the process further comprises to obtain a performance data with respect to the process and determine if the performance data is consistent with the memory contention.

18. The non-transitory computer-readable media according to claim 17, wherein the computer device is further caused to obtain the performance data from at least one of a performance monitor module in the processor or a profiling module of the computer device.

19. The non-transitory computer-readable media according to claim 17, wherein to determine if the performance data is consistent with the memory contention comprises to determine if a central processing unit process utilization threshold for the processor is exceeded when the process is executed.

20. The non-transitory computer-readable media according to claim 19, wherein to determine if the performance data is consistent with the memory contention further comprises at least one of to determine that the process comprises a loop body with assembly or machine instructions greater than an assembly or machine instruction threshold or to determine that the process comprises an atomic instruction or an atomic group of instructions.

21. The non-transitory computer-readable media according to claim 16, wherein the computer device is further caused to determine whether the transactional process may be executed by a hardware-based transactional execution process.

22. The non-transitory computer-readable media according to claim 21, wherein the hardware-based transactional execution process comprises a lock elision.

23. The non-transitory computer-readable media according to claim 22, wherein the lock elision comprises at least one of a hardware lock elision or a restricted transactional memory.

24. The non-transitory computer-readable media according to claim 16, wherein to re-write the process to form the transactional process comprises to decode a critical code region of the process, to identify regular lock/unlock instruction in the critical code region, to determine a code representation of the critical code region, wherein the code representation of the critical code region comprises a transactional lock acquire and a transactional lock release, to determine a binary machine code corresponding to the code representation of the critical code region as the transactional process, and to store the transactional process in at least one of a register or a stack of the computer device for execution.

25. The non-transitory computer-readable media according to claim 16, wherein the speculative execution results in one of an atomic commit with respect to the transactional process or ignoring the result of the transactional process.