Hardware error detection on a high-speed serial connection

• US 10,642,673 B2
• Filed: 01/02/2018
• Issued: 05/05/2020
• Est. Priority Date: 01/02/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ziebarth, Donald J., Ekman, Jeremy T., Timpane, Trevor J., Zettles, IV, George R.
• Primary Examiner(s): Amoroso, Anthony J
• Application Number:
  US15/860,201
• Publication Number:
  US 20190205194A1
• Time in Patent Office: 854 Days
• CPC Class Codes: G06F 11/0745 in an input/output transactions management context input/output processing in general G06F13/00
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 13/4291 using a clocked protocol
• CPC Class Codes: G06F 2213/0008 High speed serial bus, e.g. Fiber channel
• CPC Class Codes: G06F 2213/0016 Inter-integrated circuit (I2C)

Abstract

Hardware error detection on a high-speed serial (HSS) connection including tracking, by a hardware state machine on a HSS receiver, errors in a data stream, wherein tracking, by the hardware state machine, the errors in the data stream comprises, for each sample of incoming data: inspecting, by the hardware state machine, a detected error indicator in a test control register to determine whether an error has been detected in the sample; incrementing, by the hardware state machine, an error count in a hardware error counter if the test control register indicates an error has been detected in the sample; clearing, by the hardware state machine, the detected error indicator if the test control register indicates an error has been detected in the sample; and incrementing, by the hardware state machine, a sample count in a sample count register.

Claims

1. A method of hardware error detection on a high-speed serial (HSS) connection, the method comprising:

tracking, by a hardware state machine on a HSS receiver, errors in a data stream, wherein each sample of incoming data being tracked by the hardware state machine has been tested for errors by error detecting logic, and wherein tracking, by the hardware state machine, the errors in the data stream comprises, for each sample of incoming data;

inspecting, by the hardware state machine, a detected error indicator in a test control register to determine whether an error has been detected in the sample;

incrementing, by the hardware state machine, an error count in a hardware error counter if the test control register indicates an error has been detected in the sample;

clearing, by the hardware state machine, the detected error indicator if the test control register indicates an error has been detected in the sample; and

incrementing, by the hardware state machine, a sample count in a sample count register; and

providing, by the hardware state machine to firmware on the HSS receiver, an error rate for the data stream based on the error count in the hardware error counter and the sample count in the sample count register.

2. The method of claim 1, wherein the hardware state machine is a hardware component of an integrated circuit within the HSS receiver, and wherein the integrated circuit further comprises a high-speed serializer/deserializer operating at a physical layer of a high-speed serial protocol.

3. The method of claim 1, wherein incrementing, by the hardware state machine, the error count in the hardware error counter comprises pulsing an input signal for the hardware error counter for at least one clock cycle.

4. The method of claim 1, wherein incrementing, by the hardware state machine, the sample count in the sample count register comprises pulsing an input signal for the sample count register for at least one clock cycle.

5. The method of claim 1, wherein inspecting, by the hardware state machine, the detected error indicator in the test control register to determine whether an error has been detected in the sample comprises inspecting, by the hardware state machine, a pattern synchronization indicator to determine whether a test is active.

6. The method of claim 1, further comprising:

determining, by the HSS receiver, that the error rate exceeds an error rate threshold; and

generating, by the HSS receiver, an alert indicating that the error rate exceeds the error rate threshold.

7. The method of claim 1, wherein the hardware state machine, the test control register, the hardware error counter, and the sample count register are hardware components of an integrated circuit within the HSS receiver, and wherein the hardware state machine comprises four states:

state A, state B, state C, and state D, wherein;

state A corresponds with inspecting, by the hardware state machine, the detected error indicator in the test control register to determine whether an error has been detected in the sample;

state B corresponds with incrementing, by the hardware state machine, the error count in the hardware error counter;

state C corresponds with clearing, by the hardware state machine, the detected error indicator; and

state D corresponds with incrementing, by the hardware state machine, the sample count in the sample count register.

8. An integrated circuit for hardware error detection on a high-speed serial (HSS) connection, wherein the integrated circuit comprises a hardware state machine on a HSS receiver, and wherein the integrated circuit is configured to carry out the steps of:

tracking, by the hardware state machine, errors in a data stream, wherein each sample of incoming data being tracked by the hardware state machine has been tested for errors by error detecting logic, wherein tracking, by the hardware state machine, the errors in the data stream comprises, for each sample of incoming data;

inspecting, by the hardware state machine, a detected error indicator in a test control register to determine whether an error has been detected in the sample;

incrementing, by the hardware state machine, an error count in a hardware error counter if the test control register indicates an error has been detected in the sample;

clearing, by the hardware state machine, the detected error indicator if the test control register indicates an error has been detected in the sample; and

incrementing, by the hardware state machine, a sample count in a sample count register; and

providing, by the hardware state machine to firmware on the HSS receiver, an error rate for the data stream based on the error count in the hardware error counter and the sample count in the sample count register.

9. The integrated circuit of claim 8, wherein the hardware state machine is a hardware component of an integrated circuit within the HSS receiver, and wherein the integrated circuit further comprises a high-speed serializer/deserializer operating at a physical layer of a high-speed serial protocol.

10. The integrated circuit of claim 8, wherein incrementing, by the hardware state machine, the error count in the hardware error counter comprises pulsing an input signal for the hardware error counter for at least one clock cycle.

11. The integrated circuit of claim 8, wherein incrementing, by the hardware state machine, the sample count in the sample count register comprises pulsing an input signal for the sample count register for at least one clock cycle.

12. The integrated circuit of claim 8, wherein inspecting, by the hardware state machine, the detected error indicator in the test control register to determine whether an error has been detected in the sample comprises inspecting, by the hardware state machine, a pattern synchronization indicator to determine whether a test is active.

13. The integrated circuit of claim 8, further comprising:

determining, by the HSS receiver, that the error rate exceeds an error rate threshold; and

generating, by the HSS receiver, an alert indicating that the error rate exceeds the error rate threshold.

14. The integrated circuit of claim 8, wherein the hardware state machine, the test control register, the hardware error counter, and the sample count register are hardware components of an integrated circuit within the HSS receiver, and wherein the hardware state machine comprises four states:

state A, state B, state C, and state D, wherein;

state A corresponds with inspecting, by the hardware state machine, the detected error indicator in the test control register to determine whether an error has been detected in the sample;

state B corresponds with incrementing, by the hardware state machine, the error count in the hardware error counter;

state C corresponds with clearing, by the hardware state machine, the detected error indicator; and

state D corresponds with incrementing, by the hardware state machine, the sample count in the sample count register.

15. A computer program product for hardware error detection on a high-speed serial (HSS) connection, the computer program product disposed upon a computer readable medium, the computer program product comprising computer program instructions that, when executed, cause an integrated circuit to carry out the steps of:

tracking, by a hardware state machine on a HSS receiver, errors in a data stream, wherein each sample of incoming data being tracked by the hardware state machine has been tested for errors by error detecting logic, wherein tracking, by the hardware state machine, the errors in the data stream comprises, for each sample of incoming data;

inspecting, by the hardware state machine, a detected error indicator in a test control register to determine whether an error has been detected in the sample;

incrementing, by the hardware state machine, an error count in a hardware error counter if the test control register indicates an error has been detected in the sample;

clearing, by the hardware state machine, the detected error indicator if the test control register indicates an error has been detected in the sample; and

incrementing, by the hardware state machine, a sample count in a sample count register; and

providing, by the hardware state machine to firmware on the HSS receiver, an error rate for the data stream based on the error count in the hardware error counter and the sample count in the sample count register.

16. The computer program product of claim 15, wherein the hardware state machine is a hardware component of an integrated circuit within the HSS receiver, and wherein the integrated circuit further comprises a high-speed serializer/deserializer operating at a physical layer of a high-speed serial protocol.

17. The computer program product of claim 15, wherein incrementing, by the hardware state machine, the error count in the hardware error counter comprises pulsing an input signal for the hardware error counter for at least one clock cycle.

18. The computer program product of claim 15, wherein incrementing, by the hardware state machine, the sample count in the sample count register comprises pulsing an input signal for the sample count register for at least one clock cycle.

19. The computer program product of claim 15, wherein inspecting, by the hardware state machine, the detected error indicator in the test control register to determine whether an error has been detected in the sample comprises inspecting, by the hardware state machine, a pattern synchronization indicator to determine whether a test is active.

20. The computer program product of claim 15, further comprising:

determining, by the HSS receiver, that the error rate exceeds an error rate threshold; and

generating, by the HSS receiver, an alert indicating that the error rate exceeds the error rate threshold.