Hardware error detection on a high-speed serial connection
First Claim
1. A method of hardware error detection on a high-speed serial (HSS) connection, the method comprising:
- tracking, by a hardware state machine on a HSS receiver, errors in a data stream, wherein each sample of incoming data being tracked by the hardware state machine has been tested for errors by error detecting logic, and wherein tracking, by the hardware state machine, the errors in the data stream comprises, for each sample of incoming data;
inspecting, by the hardware state machine, a detected error indicator in a test control register to determine whether an error has been detected in the sample;
incrementing, by the hardware state machine, an error count in a hardware error counter if the test control register indicates an error has been detected in the sample;
clearing, by the hardware state machine, the detected error indicator if the test control register indicates an error has been detected in the sample; and
incrementing, by the hardware state machine, a sample count in a sample count register; and
providing, by the hardware state machine to firmware on the HSS receiver, an error rate for the data stream based on the error count in the hardware error counter and the sample count in the sample count register.
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Accused Products
Abstract
Hardware error detection on a high-speed serial (HSS) connection including tracking, by a hardware state machine on a HSS receiver, errors in a data stream, wherein tracking, by the hardware state machine, the errors in the data stream comprises, for each sample of incoming data: inspecting, by the hardware state machine, a detected error indicator in a test control register to determine whether an error has been detected in the sample; incrementing, by the hardware state machine, an error count in a hardware error counter if the test control register indicates an error has been detected in the sample; clearing, by the hardware state machine, the detected error indicator if the test control register indicates an error has been detected in the sample; and incrementing, by the hardware state machine, a sample count in a sample count register.
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Citations
20 Claims
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1. A method of hardware error detection on a high-speed serial (HSS) connection, the method comprising:
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tracking, by a hardware state machine on a HSS receiver, errors in a data stream, wherein each sample of incoming data being tracked by the hardware state machine has been tested for errors by error detecting logic, and wherein tracking, by the hardware state machine, the errors in the data stream comprises, for each sample of incoming data; inspecting, by the hardware state machine, a detected error indicator in a test control register to determine whether an error has been detected in the sample; incrementing, by the hardware state machine, an error count in a hardware error counter if the test control register indicates an error has been detected in the sample; clearing, by the hardware state machine, the detected error indicator if the test control register indicates an error has been detected in the sample; and
incrementing, by the hardware state machine, a sample count in a sample count register; andproviding, by the hardware state machine to firmware on the HSS receiver, an error rate for the data stream based on the error count in the hardware error counter and the sample count in the sample count register. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An integrated circuit for hardware error detection on a high-speed serial (HSS) connection, wherein the integrated circuit comprises a hardware state machine on a HSS receiver, and wherein the integrated circuit is configured to carry out the steps of:
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tracking, by the hardware state machine, errors in a data stream, wherein each sample of incoming data being tracked by the hardware state machine has been tested for errors by error detecting logic, wherein tracking, by the hardware state machine, the errors in the data stream comprises, for each sample of incoming data; inspecting, by the hardware state machine, a detected error indicator in a test control register to determine whether an error has been detected in the sample; incrementing, by the hardware state machine, an error count in a hardware error counter if the test control register indicates an error has been detected in the sample; clearing, by the hardware state machine, the detected error indicator if the test control register indicates an error has been detected in the sample; and incrementing, by the hardware state machine, a sample count in a sample count register; and providing, by the hardware state machine to firmware on the HSS receiver, an error rate for the data stream based on the error count in the hardware error counter and the sample count in the sample count register. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A computer program product for hardware error detection on a high-speed serial (HSS) connection, the computer program product disposed upon a computer readable medium, the computer program product comprising computer program instructions that, when executed, cause an integrated circuit to carry out the steps of:
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tracking, by a hardware state machine on a HSS receiver, errors in a data stream, wherein each sample of incoming data being tracked by the hardware state machine has been tested for errors by error detecting logic, wherein tracking, by the hardware state machine, the errors in the data stream comprises, for each sample of incoming data; inspecting, by the hardware state machine, a detected error indicator in a test control register to determine whether an error has been detected in the sample; incrementing, by the hardware state machine, an error count in a hardware error counter if the test control register indicates an error has been detected in the sample; clearing, by the hardware state machine, the detected error indicator if the test control register indicates an error has been detected in the sample; and incrementing, by the hardware state machine, a sample count in a sample count register; and providing, by the hardware state machine to firmware on the HSS receiver, an error rate for the data stream based on the error count in the hardware error counter and the sample count in the sample count register. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification