Inner and outer code generator for volatile memory

• US 10,642,683 B2
• Filed: 10/11/2017
• Issued: 05/05/2020
• Est. Priority Date: 10/11/2017
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Inventors: Dropps, Frank R.
• Primary Examiner(s): Manoskey, Joseph D
• Application Number:
  US15/729,891
• Publication Number:
  US 20190108147A1
• Time in Patent Office: 937 Days
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/102 Error in check bits
• CPC Class Codes: G06F 11/1056 Updating check bits on partial write, i.e. read/modify/write
• CPC Class Codes: G06F 11/106 Correcting systematically all correctable errors, i.e. scrubbing
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 8/37 Compiler construction; Parser generation
• CPC Class Codes: G06F 8/65 Updates security arrangements therefor G06F21/57

Abstract

A system includes a volatile memory to store data and a memory controller to manage the data in the volatile memory. The memory controller includes an inner code generator to generate a respective inner correction code for each of a plurality of blocks of the data in the volatile memory. An outer code generator generates an outer correction code based on the plurality of blocks of the data. The memory controller updates the outer correction code as part of a refresh to the plurality of blocks of the data in the volatile memory.

Claims

1. A system, comprising:

a volatile memory to store data;

a memory controller to manage the data in the volatile memory, the memory controller comprising;

an inner code generator to generate a respective inner correction code for each of a plurality of blocks of the data in the volatile memory;

an outer code generator to generate an outer correction code based on the plurality of blocks of the data, wherein the memory controller updates the outer correction code as part of a refresh to the plurality of blocks of the data in the volatile memory; and

a memory scrubber to correct single bit errors via the inner correction code in the plurality of blocks of the data and to correct multiple bit errors via the outer correction code in the plurality of blocks of the data; and

wherein the memory controller specifies a length N of bytes for the plurality of blocks of the data, if the memory controller updates all N bytes for the plurality of blocks of the data, the inner correction code is updated for the N bytes and the outer correction code is updated based on the updates to the N bytes, N being a positive integer, the inner correction code and the outer correction code being updated as part of the refresh to the data.

2. The system of claim 1, wherein if the memory controller updates less than the length N of bytes specified for the plurality of blocks of data, a flag is set indicating the outer correction code is invalid and the memory scrubber monitors the flag and updates the outer correction code based on the partial write initiated to the plurality of blocks of the data.

3. The system of claim 2, wherein the outer code generator updates the outer correction code and the memory scrubber resets the flag to valid after the length of N bytes has been updated or read by the memory controller.

4. The system of claim 1, wherein the inner code generator processes the plurality of blocks of the data and generates an error checking and correction code (ECC) as the inner correction code for each block of the data.

5. The system of claim 4, wherein the outer code generator processes the block of data and generates a parity code, a Cycle Redundancy Check (CRC) code, a Hamming code, a Bose-Chaudhuri-Hocquenghem (BCH) code, a low density parity check (LDPC) code, or a Reed-Solomon code as the outer correction code.

6. The system of claim 4, wherein the inner code generator generates the ECC for the outer correction code to facilitate error correction of the outer correction code.

7. The system of claim 6, wherein the memory controller is a cache memory controller that controls memory updates and refresh to the volatile memory, and wherein the plurality of blocks of the data form a respective cache line of the volatile memory.

8. The system of claim 7, wherein the volatile memory is a dynamic random access memory (DRAM).

9. A method, comprising:

generating an inner correction code for each of a plurality of data blocks of volatile memory;

generating an outer correction code based on processing the plurality of data blocks collectively;

refreshing the volatile memory that includes the plurality of data blocks, the outer correction code being updated as part of the refreshing;

correcting a single bit error via the respective inner correction code in response to detecting the single bit error in one of the plurality of data blocks;

correcting a multiple bit error via the outer correction code in response to detecting the multiple bit error in a given data block in the plurality of data blocks;

specifying a length N of bytes for the block of data, N being a positive integer;

updating all N bytes for the block of data;

updating the inner correction code for the N bytes and the outer correction code based on the updating to the N bytes;

updating less than the length N of bytes specified for the block of data; and

setting a flag indicating that a partial write has been initiated to update the block of data and that the outer correction code is invalid.

10. The method of claim 9, further comprising:

updating the outer correction code and

resetting the flag to valid after the length of N bytes has been updated or read.

11. A system, comprising:

a volatile memory to store data; and

a memory controller to manage the data in the volatile memory, the memory controller comprising;

an inner code generator to generate a plurality of inner correction codes based on data values in each of a plurality of data blocks in the volatile memory, wherein each of the plurality of inner correction codes is assigned to correct a respective one of the plurality of data blocks;

an outer code generator to generate an outer correction code based on processing the plurality of data blocks collectively, wherein the memory controller updates at least one of the inner correction code and the outer correction code during a refresh to the plurality of data blocks in the volatile memory; and

a memory scrubber to correct single bit errors in a given one of the plurality of data blocks via its respective inner correction code and to correct multiple bit errors in the plurality data blocks via the outer correction code; and

wherein the memory scrubber monitors a flag indicating a partial memory write has occurred to a subset of the data blocks and the outer code generator updates the outer correction code based on the partial memory write.

12. A system, comprising:

a volatile memory to store data; and

a memory controller to manage the data in the volatile memory, the memory controller comprising;

an inner code generator to generate a respective inner correction code for each of a plurality of blocks of the data in the volatile memory; and

an outer code generator to generate an outer correction code based on the plurality of blocks of the data, wherein the memory controller updates the outer correction code as part of a refresh to the plurality of blocks of the data in the volatile memory; and

wherein;

the inner code generator processes the plurality of blocks of the data and generates an error checking and correction code (ECC) as the inner correction code for each block of the data; and

the inner code generator generates the ECC for the outer correction code to facilitate error correction of the outer correction code.

13. The system of claim 12, wherein the memory controller further comprises a memory scrubber to correct single bit errors via the inner correction code in the plurality of blocks of the data and to correct multiple bit errors via the outer correction code in the plurality of blocks of the data.

14. The system of claim 13, wherein if the memory controller updates less than a length N of bytes specified for the plurality of blocks of data, a flag is set indicating the outer correction code is invalid and the memory scrubber monitors the flag and updates the outer correction code based on the partial write initiated to the plurality of blocks of the data.

15. The system of claim 14, wherein the outer code generator updates the outer correction code and the memory scrubber resets the flag to valid after the length of N bytes has been updated or read by the memory controller.

16. The system of claim 12, wherein the outer code generator processes the block of data and generates a parity code, a Cycle Redundancy Check (CRC) code, a Hamming code, a Bose-Chaudhuri-Hocquenghem (BCH) code, a low density parity check (LDPC) code, or a Reed-Solomon code as the outer correction code.