Memory command interleaving

• US 10,642,684 B1
• Filed: 06/28/2018
• Issued: 05/05/2020
• Est. Priority Date: 06/28/2018
• Status: Active Grant

• Current Assignee: AT&T Intellectual Property I LP (AT&T, Inc.), Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: MacLaren, John M., Hughes, Anne, Shepherd, Thomas J., Olson, Carl Nels
• Primary Examiner(s): Alphonse, Fritz
• Application Number:
  US16/022,276
• Time in Patent Office: 677 Days
• Field of Search: 714764, 714766, 714767, 714770
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1056 Updating check bits on partial write, i.e. read/modify/write
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling

Abstract

Various embodiments described herein provide for grouping read-modify-writes (RMWs) such that multiple RMW command sequences can be executed (or rearranged in the command queue) in an interleaved manner rather than being executed in order. In particular, various embodiments described herein split the read and write components (commands) of multiple RMW command sequences, group the read components in the command queue to execute consecutively, and group the write components in the command queue to execute consecutively.

Claims

1. A memory controller comprising:

a command queue component configured to provide a command queue storing a plurality of memory commands for timely execution by the memory controller; and

a read-modify-write component configured to perform operations comprising;

analyzing the command queue for read-modify-write command sequences;

based on the analyzing the command queue;

placing, in the command queue, read commands of a plurality of read-modify-write command sequences as a read-modify-write group of consecutive read commands; and

placing;

in the command queue, write commands of the plurality of read-modify-write command sequences as a read-modify-write group of consecutive write commands.

2. The memory controller of claim 1, wherein the read-modify-write group consecutive reads commands is placed in the command queue to execute prior to the read-modify-write group of consecutive write commands.

3. The memory controller of claim 1, wherein the read-modify-write component is further configured to perform operations comprising:

based on the analyzing the command queue;

allocating a read-modify-write buffer for each read command in the read-modify-write group of consecutive read commands.

4. The memory controller of claim 1, wherein the memory controller uses split addressing to generate memory commands for memory transactions with respect to a memory, the memory controller causes the memory to store primary data inline with error checking data generated for the primary data, and wherein the read-modify-write command sequences comprises at least one read-modify-write command sequence for particular primary data and at least one read-modify-write command sequence for particular error checking data that is associated with the particular primary data.

5. The memory controller of claim 4, wherein the read-modify-write component is further configured to perform operations comprising:

based on the analyzing the command queue;

allocating a read-modify-write buffer for each read command for primary data in the read-modify-write group of consecutive read commands; and

allocating an error checking data buffer for each read command for error checking data in the read-modify-write group of consecutive read commands.

6. The memory controller of claim 5, wherein the error checking data comprises error correcting code (ECC).

7. The memory controller of claim 1, wherein the read-modify-write component further configured to perform operations comprising:

based on the analyzing the command queue;

determining whether a predetermined maximum number of read-modify-writes has been reached or exceeded; and

in response to determining that the predetermined maximum number of read-modify-writes has been reached or exceeded, setting a watermark bit in the command queue.

8. The memory controller of claim 7, wherein the watermark bit is set with respect to an entry, in the command queue, associated with at least a last write command in the read-modify-write group of consecutive write commands.

9. The memory controller of claim 7, wherein the determining whether the predetermined maximum number of read-modify-writes has been reached or exceeded is based on a counter that tracks a number of write commands in the read-modify-write group of consecutive write commands.

10. The memory controller of claim 7, wherein the read-modify-write component is further configured to perform operations comprising:

in response to determining that the predetermined maximum number of read-modify-writes has been reached or exceeded, placing a subsequent read-modify-write command sequence in the command queue such that the subsequent read-modify-write command sequence executes after execution of the read-modify-write group of consecutive write commands.

11. The memory controller of claim 10, wherein the placing the subsequent read-modify-write command sequence in the command queue such that the subsequent read-modify-write command sequence executes after execution of the read-modify-write group of consecutive write commands comprises placing the subsequent read-modify-write command sequence in the command queue behind at least a last entry in the command queue having a set watermark bit.

12. A method comprising:

evaluating, by a memory controller, placement of a read-modify-write command sequence in a command queue, the evaluating comprising determining whether a predetermined maximum number of read-modify-writes has been reached; and

in response to determining that the predetermined maximum number of read-modify-writes has not been reached or exceeded;

placing, by the memory controller, a first read command of the read-modify-write command sequence in the command queue as part of a read-modify-write group of consecutive read commands in the command queue; and

placing, by the memory controller, a first write command of the read-modify-write command sequence in the command queue as part of a read-modify-write group of consecutive write commands.

13. The method of claim 12, further comprising:

in response to determining that the predetermined maximum number of read-modify-writes has not been reached or exceeded;

allocating, by the memory-controller, a read-modify-write buffer for the read-modify-write command sequence.

14. The method of claim 12;

further comprising;

in response to determining that the predetermined maximum number of read-modify-writes has been reached or exceeded, setting, by the memory controller, a watermark bit in the command queue.

15. The method of claim 14, wherein the watermark bit is set with respect to an entry, in the command queue, associated with at least a last write command in the read-modify-write group of consecutive write commands.

16. The method of claim 12, further comprising:

in response to determining that the predetermined maximum number of read-modify-writes has been reached or exceeded, placing, by the memory controller, the read-modify-write command sequence in the command queue such that the read-modify-write command sequence executes after execution of the read-modify-write group of consecutive write commands.

17. The method of claim 16, wherein the placing the read-modify-write command sequence in the command queue such that the read-modify-write command sequence executes after execution of the read-modify-write group of consecutive write commands comprises placing the read-modify-write command sequence in the command queue behind at least a last entry in the command queue having a set watermark bit.

18. The method of claim 12, wherein the determining whether the predetermined maximum number of read-modify-writes has been reached or exceeded is based on a counter that tracks a number of write commands in the read-modify-write group of consecutive write commands.

19. A method comprising:

storing, on a memory, primary data inline with error checking data generated for the primary data using split addressing for memory transactions, the primary data being stored on the memory at a range of inline primary data addresses and the error checking data being stored on the memory at a range of inline error checking data addresses, the range of inline primary data addresses not overlapping with the range of inline error checking data addresses;

generating, by a memory controller and based on a requested memory transaction, a first read-modify-write command sequence for particular primary data and a second read-modify-write command sequence for particular error checking data, the particular error checking data being generated for the particular primary data;

evaluating, by the memory controller, placement of the first and second read-modify-write command sequences in a command queue, the evaluating placement comprising determining whether a predetermined maximum number of read-modify-writes has been reached;

in response to determining that the predetermined maximum number of read-modify-writes has not been reached or exceeded;

placing, by the memory controller, both a first read command of the first read-modify-write command sequence and a second read command of the second read-modify-write command sequence in the command queue as part of a read-modify-write group of consecutive read commands in the command queue; and

placing, by the memory controller, both a first write command of the first read-modify-write command sequence and a second write command of the second read-modify-write command sequence in the command queue as part of a read-modify-write group of consecutive write commands.

20. The method of claim 19, further comprising:

in response to determining that the predetermined maximum number of read-modify-writes has been reached or exceeded, placing, by the memory controller, both the first read-modify-write command sequence and the second read-modify-write command sequence in the command queue such that both the first read-modify-write command sequence and the second read-modify-write command sequence execute after execution of the read-modify-write group of consecutive write commands.