Storage backed memory package save trigger

• US 10,642,695 B2
• Filed: 08/21/2018
• Issued: 05/05/2020
• Est. Priority Date: 02/08/2018
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Dunn, James E., Eckel, Nathan A.
• Primary Examiner(s): Rones, Charles
• Assistant Examiner(s): Li, Hewy H
• Application Number:
  US16/107,259
• Publication Number:
  US 20190243713A1
• Time in Patent Office: 623 Days
• Field of Search: None
• CPC Class Codes: G06F 11/0778 Dumping, i.e. gathering error/state information after a fault for later diagnosis
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 11/1456 Hardware arrangements for backup
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 2213/0016 Inter-integrated circuit (I2C)
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/4072 Circuits for initialization, powering up or down, clearing memory or presetting
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits
• CPC Class Codes: G11C 7/20 Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Abstract

Devices and techniques for a storage backed memory package save trigger are disclosed herein. Data can be received via a first interface. The data is stored in a volatile portion of the memory package. Here, the memory package includes a second interface arranged to connect a host to a controller in the memory package. A reset signal can be received at the memory package via the first interface. The data stored in the volatile portion of the memory package can be saved to a non-volatile portion of the memory package in response to the reset signal.

Claims

1. A memory package, the memory package comprising:

a volatile portion arranged to store data;

a non-volatile portion;

a first interface comprising a version four double data rate (DDR4) random-access memory (RAM) interface, the first interface being arranged to;

receive the data; and

receive a reset signal at a pin corresponding to RESET_n as defined in a Joint Electron Device Engineering Council (JEDEC) family of standards for version four double data rate (DDR4);

a second interface arranged to connect to a host; and

a processing device arranged to save the data stored in the volatile portion to the non-volatile portion in response to the reset signal.

2. The memory package of claim 1, wherein the second interface comprises a bus that operates in accordance with an Inter-Integrated Circuit (I2C) family of standards.

3. The memory package of claim 1, wherein the processing device is arranged to save the data stored in the volatile portion to the non-volatile portion in response to a determination that a dedicated save signal is inoperative.

4. The memory package of claim 3, wherein the dedicated save signal is communicated by a second pin corresponding to SAVE_n as defined in the Joint Electron Device Engineering Council (JEDEC) family of standards for version four double data rate (DDR4).

5. The memory package of claim 1, wherein the processing device is arranged to save the data stored in the volatile portion to the non-volatile portion in response to a self-refresh mode of the memory package being enabled at a time of the reset signal.

6. A method comprising:

receiving data via a first interface to store in a volatile portion of a memory package, the first interface comprising a version four double data rate (DDR4) random-access memory (RAM) interface, the memory package including a second interface arranged to connect a host to a processing device in the memory package;

receiving a reset signal at a pin of the first interface, the pin corresponding to RESET_n as defined in a Joint Electron Device Engineering Council (JEDEC) family of standards for version four double data rate (DDR4); and

saving the data stored in the volatile portion of the memory package to a non-volatile portion of the memory package in response to the reset signal.

7. The method of claim 6, wherein the second interface comprises a bus that operates in accordance with an Inter-Integrated Circuit (I2C) family of standards.

8. The method of claim 6, wherein saving the data stored in the volatile portion of the memory package to the non-volatile portion of the memory package is performed in response to a determination that a dedicated save signal is inoperative.

9. The method of claim 8, wherein the dedicated save signal is communicated by a second pin corresponding to SAVE_n as defined in the Joint Electron Device Engineering Council (JEDEC) family of standards for version four double data rate (DDR4).

10. The method of claim 6, wherein saving the data stored in the volatile portion of the memory package to the non-volatile portion of the memory package is performed in response to a self-refresh mode of the memory package being enabled at a time of the reset signal.

11. At least one machine readable medium including instructions, the instructions, when executed by processing circuitry of a memory package, cause the memory package to perform operations comprising:

receiving data via a first interface to store in a volatile portion of the memory package, the first interface comprising a version four double data rate (DDR4) random-access memory (RAM) interface, the memory package including a second interface arranged to connect a host to a processing device in the memory package;

receiving a reset signal at a pin of the first interface, the pin corresponding to RESET_n as defined in a Joint Electron Device Engineering Council (JEDEC) family of standards for version four double data rate (DDR4); and

saving the data stored in the volatile portion of the memory package to a non-volatile portion of the memory package in response to the reset signal.

12. The at least one machine readable medium of claim 11, wherein the second interface comprises a bus that operates in accordance with an I2C family of standards.

13. The at least one machine readable medium of claim 11, wherein saving the data stored in the volatile portion of the memory package to the non-volatile portion of the memory package is performed in response to a determination that a dedicated save signal is inoperative.

14. The at least one machine readable medium of claim 13, wherein the dedicated save signal is communicated by a second pin corresponding to SAVE_n as defined in the Joint Electron Device Engineering Council (JEDEC) family of standards for version four double data rate (DDR4).

15. The at least one machine readable medium of claim 11, wherein saving the data stored in the volatile portion of the memory package to the non-volatile portion of the memory package is performed in response to a self-refresh mode of the memory package being enabled at a time of the reset signal.