Managing migration events performed by a memory controller

• US 10,642,727 B1
• Filed: 09/27/2017
• Issued: 05/05/2020
• Est. Priority Date: 09/27/2017
• Status: Active Grant

• Current Assignee: Amazon Technologies, Inc. (Amazon.com, Inc.)
• Original Assignee: Amazon Technologies, Inc. (Amazon.com, Inc.)
• Inventors: Volpe, Thomas A., Banse, Mark Anthony, Larson, Steven Scott
• Primary Examiner(s): Duncan, Marc
• Assistant Examiner(s): Gibson, Jonathan D
• Application Number:
  US15/717,763
• Time in Patent Office: 951 Days
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/1402 Saving, restoring, recovering or retrying
• CPC Class Codes: G06F 11/1415 at system level
• CPC Class Codes: G06F 12/0238 Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 2201/805 Real-time
• CPC Class Codes: G06F 2212/1036 Life time enhancement
• CPC Class Codes: G06F 2212/202 Non-volatile memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7211 Wear leveling

Abstract

A microcontroller may be implanted to manage migration events performed by a separate memory controller to non-volatile memory. Migration events, such as failed writes at the memory controller or wear leveling migrations to move data from one storage location to another may be detected by the microcontroller. The destination location and the data to be migrated may be identified by the microcontroller. The microcontroller may then instruct the memory controller to copy the data to the destination location.

Claims

1. A system, comprising:

a processor;

a memory, that stores program instructions that when executed by the processor cause the processor to implement a host for a virtual computing resource, wherein the host stores data for the computing resource in a non-volatile memory via an access device for the non-volatile memory;

the non-volatile memory; and

the access device for the non-volatile memory, the access device comprising a microcontroller and a memory controller;

wherein the microcontroller is configured to;

obtain an indication of a write or an attempt to write to a storage location in the non-volatile memory from the memory controller, wherein the write was received at the memory controller from the processor;

based on the indication of the write or the attempt to write to the storage location, detect a migration event for the storage location;

in response to the detection of the migration event;

identify a source location for data to migrate and a destination location in the non-volatile memory to store the data; and

send a request to the memory controller to write a copy of the data from the source location to the destination location.

2. The system of claim 1, wherein the access device further comprises a memory management unit (MMU) that maps storage locations in the non-volatile memory to different data for the processor, and wherein the microcontroller is further configured to:

after a determination that the write of the copy of the data from the source location to the destination location is successful, update the MMU to map the data to the destination location in the non-volatile memory.

3. The system of claim 1, wherein to detect the migration event for the storage location, the microcontroller is configured to:

receive an interrupt from the memory controller indicating a failed write to the storage location; and

trigger the migration event to migrate data of the failed write as the identified data.

4. The system of claim 1, wherein the non-volatile memory is a storage class memory device.

5. A method, comprising:

detecting, by a processor, a migration event for a storage location in a non-volatile memory based, at least in part, on a write or an attempt to write to the storage location by a memory controller for the non-volatile memory;

identifying, by the processor, data to migrate for the migration event and a destination location in the non-volatile memory to store the data; and

instructing, by the processor, the memory controller to write the data to the destination location in the non-volatile memory.

6. The method of claim 5, wherein detecting the migration event for the storage location comprises:

tracking write counts for a plurality of storage locations in the non-volatile memory including the storage location and the destination location;

comparing the write counts of the storage locations to a wear leveling threshold to select the storage location for migration;

based on the write counts for the storage locations, selecting the destination location; and

triggering the migration event to migrate data in the selected storage location as the data to migrate.

7. The method of claim 5, wherein detecting the migration event for the storage location comprises:

receiving an interrupt from the memory controller indicating a failed write to the storage location, wherein the write was received at the memory controller from a host processor; and

triggering the migration event to migrate data of the failed write as the identified data.

8. The method of claim 5, wherein instructing the memory controller to write the data to the destination location comprises causing performance of a Direct Memory Access (DMA) operation to write the data to the destination location.

9. The method of claim 5, further comprising:

after determining that the write to the destination location is successful, updating a memory management unit (MMU) to map the data to the destination location in the non-volatile memory.

10. The method of claim 9, wherein the MMU is implemented as part of a host processor that sent the write to the memory controller.

11. The method of claim 5, further comprising:

after determining that the write to the destination location is not successful;

selecting a different destination location in the non-volatile memory; and

instructing the memory controller to write the data to the different destination location in the non-volatile memory.

12. The method of claim 5, wherein the data to migrate is stored in an entry of a copy buffer, and wherein the method further comprises:

after determining that the data in the copy buffer was changed during the migration of the storage location;

instructing the memory controller to write the changed data from the entry in the copy buffer to the destination location in the non-volatile memory.

13. The method of claim 5, wherein the microcontroller is implemented as part of an access device for the non-volatile memory, wherein the access device is an application specific integrated circuit (ASIC), a system-on-chip (SoC), or a field-programmable gate array (FPGA), and wherein the access device is connected to a host processor.

14. A microcontroller for a non-volatile storage device, comprising:

a processor; and

a memory, storing program instructions that when executed by the processor cause the processor to;

detect a migration event for a storage location in the non-volatile memory based on a write performed to the storage location by a memory controller for the non-volatile memory;

identify a source location of data to migrate for the migration event and a destination location in the non-volatile memory to store the data;

write an indication of the source location and the destination location to a control status register accessible to the memory controller; and

send a request to the memory controller to write a copy of the data in the source location to the destination location in the non-volatile memory according to the indication in the control status register.

15. The microcontroller of claim 14, wherein to send the request to the memory controller to write the copy of the data in the source location to the destination location, the microcontroller is configured to cause performance of a Direct Memory Access (DMA) operation to write the data to the destination location.

16. The microcontroller of claim 14, wherein the microcontroller is further configured to:

after a determination that the write to the destination location is successful, update a memory management unit (MMU) to map the data to the destination location in the non-volatile memory.

17. The microcontroller of claim 14, wherein the MMU is implemented as part of a host processor that sent the write to the memory controller.

18. The microcontroller of claim 14, wherein the identified source location of the data is an entry in a copy buffer, wherein the migration event is detected for a failed write to migrate data to the storage location from another location.

19. The microcontroller of claim 14, wherein to detect the migration event for the storage location, the microcontroller is configured to:

track write counts for a plurality of storage locations in the non-volatile memory including the storage location and the destination location;

compare the write counts of the storage locations to a wear leveling threshold to select the storage location for migration;

based on the write counts for the storage locations, select the destination location; and

trigger the migration event identifying data in the selected storage location as the data to migrate.

20. The microcontroller of claim 14, wherein the microcontroller is implemented as part of an access device for the non-volatile memory, and wherein the access device is an application specific integrated circuit (ASIC), a system-on-chip (SoC), or a field-programmable gate array (FPGA).