Non-power of two memory configuration

• US 10,642,734 B1
• Filed: 12/03/2018
• Issued: 05/05/2020
• Est. Priority Date: 12/03/2018
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Pillai, Pazhani
• Primary Examiner(s): Bragdon, Reginald G
• Assistant Examiner(s): Vo, Thanh D
• Application Number:
  US16/208,139
• Time in Patent Office: 519 Days
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 12/0623 for memory modules
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/1647 with interleaved bank access
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 2212/2532 comprising a plurality of modules
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems, apparatuses, and methods for managing a non-power of two memory configuration are disclosed. A computing system includes at least one or more clients, a control unit, and a memory subsystem with a non-power of two number of active memory channels. The control unit reduces a ratio of the number of active memory channels over the total number of physical memory channels to a ratio of a first number to a second number. If a first subset of physical address bits of a received memory request are greater than or equal to the first number, the control unit calculates a third number which is equal to a second subset of physical address bits modulo the first number and the control unit uses a concatenation of the third number and a third subset of physical address bits to select a memory channel for issuing the received memory request.

Claims

1. A system comprising:

one or more clients; and

a memory subsystem having a first ratio of active memory channels to total memory channels;

wherein the memory subsystem is configured to;

reduce the first ratio to a second ratio of a first number to a second number;

receive a memory request from a client of the one or more clients;

responsive to determining that a first subset of physical address bits of the memory request have a value that is greater than or equal to the first number;

calculate a third number based on a value corresponding to a second subset of physical address bits modulo the first number;

select a memory channel, of a plurality of memory channels, using a concatenation of the third number and a third subset of physical address bits; and

complete the memory request to the selected memory channel.

2. The system as recited in claim 1, wherein responsive to determining that the first subset of physical address bits of the memory request have a value that is greater than or equal to the first number, the control unit is further configured to:

calculate a fourth number which is based on the first subset of physical address bits shifted up by a fifth number, wherein the fifth number is calculated based on a size of an address space of the memory subsystem;

calculate a first subset of normalized address bits as being equal to the second subset of physical address bits with upper bits being replaced by the first subset of physical address bits;

calculate a second subset of normalized address bits as being equal to a concatenation of a fourth subset of physical address bits and a fifth subset of physical address bits; and

complete the memory request to a normalized address on the selected memory channel, wherein the normalized address comprises the first subset of normalized address bits and the second subset of normalized address bits.

3. The system as recited in claim 2, wherein the memory subsystem has a non-power of two number of active memory channels.

4. The system as recited in claim 3, wherein the first subset of physical address bits are adjacent to the third subset of physical address bits.

5. The system as recited in claim 4, wherein the fourth subset of physical address bits are adjacent to the first subset of physical address bits.

6. The system as recited in claim 5, wherein the third subset of physical address bits are adjacent to the fifth subset of physical address bits.

7. The system as recited in claim 1, wherein the one or more clients are graphics engines, and wherein the memory request is generated as part of an application for rendering pixels to be displayed on a display.

8. A method comprising:

determining, by a control unit of a first device, a number of active memory channels out of a total number of physical memory channels in a memory subsystem;

reducing a ratio of the number of active memory channels to the total number of physical memory channels down from a first number to a second number;

responsive to determining that a first subset of physical address bits of a received memory request are greater than or equal to the first number;

calculating a third number which is based on a value corresponding to a second subset of physical address bits modulo the first number;

selecting a memory channel, of a plurality of memory channels, using a concatenation of the third number and a third subset of physical address bits; and

completing the memory request to the selected memory channel.

9. The method as recited in claim 8, wherein responsive to determining that the first subset of physical address bits of the memory request are greater than or equal to the first number, the method further comprising:

calculating a fourth number which is based on the first subset of physical address bits shifted up by a fifth number, wherein the fifth number is calculated based on a size of an address space of the memory subsystem;

calculating a first subset of normalized address bits as being equal to the second subset of physical address bits with upper bits being replaced by the first subset of physical address bits;

calculating a second subset of normalized address bits as being equal to a concatenation of a fourth subset of physical address bits and a fifth subset of physical address bits; and

completing the memory request to a normalized address on the selected memory channel, wherein the normalized address comprises the first subset of normalized address bits and the second subset of normalized address bits.

10. The method as recited in claim 9, wherein the memory subsystem has a non-power of two number of active memory channels.

11. The method as recited in claim 10, wherein the first subset of physical address bits are adjacent to the third subset of physical address bits.

12. The method as recited in claim 11, wherein the fourth subset of physical address bits are adjacent to the first subset of physical address bits.

13. The method as recited in claim 12, wherein the third subset of physical address bits are adjacent to the fifth subset of physical address bits.

14. The method as recited in claim 8, further comprising generating the memory request as part of an application for rendering pixels to be displayed on a display.

15. An apparatus comprising:

a control unit; and

a memory subsystem comprising a plurality of memory channels;

wherein the control unit is configured to;

determine a number of active memory channels out of a total number of physical memory channels in the memory subsystem;

reduce a ratio of the number of active memory channels to the total number of physical memory channels down from a first number to a second number;

responsive to determining a first subset of physical address bits of a received memory request are greater than or equal to the first number;

calculate a third number which is based on a second subset of physical address bits modulo the first number;

select a memory channel, of the plurality of memory channels, using a concatenation of the third number and a third subset of physical address bits; and

complete the memory request to the selected memory channel.

16. The apparatus as recited in claim 15, wherein responsive to determining a first subset of physical address bits of the memory request are greater than or equal to the first number, the control unit is further configured to:

calculate a fourth number which is based on the first subset of physical address bits shifted up by a fifth number, wherein the fifth number is calculated based on a size of an address space of the memory subsystem;

calculate a first subset of normalized address bits as being equal to the second subset of physical address bits with upper bits being replaced by the first subset of physical address bits;

calculate a second subset of normalized address bits as being equal to a concatenation of a fourth subset of physical address bits and a fifth subset of physical address bits; and

complete the memory request to a normalized address on the selected memory channel, wherein the normalized address comprises the first subset of normalized address bits and the second subset of normalized address bits.

17. The apparatus as recited in claim 16, wherein the memory subsystem has a non-power of two number of active memory channels.

18. The apparatus as recited in claim 17, wherein the first subset of physical address bits are adjacent to the third subset of physical address bits.

19. The apparatus as recited in claim 18, wherein the fourth subset of physical address bits are adjacent to the first subset of physical address bits.

20. The apparatus as recited in claim 19, wherein the third subset of physical address bits are adjacent to the fifth subset of physical address bits.