Efficient cache memory having an expiration timer

• US 10,642,736 B2
• Filed: 01/31/2019
• Issued: 05/05/2020
• Est. Priority Date: 06/27/2017
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Tosaka, Eiji
• Primary Examiner(s): Patel, Kaushikkumar M
• Application Number:
  US16/264,263
• Publication Number:
  US 20190163629A1
• Time in Patent Office: 460 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0808 with cache invalidating means G06F12/0815 takes precedence
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 12/128 adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/303 In peripheral interface, e.g. I/O adapter or channel
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling

Abstract

In one embodiment, a method includes selectively invalidating data stored in at least one cache line of a cache memory in response to a determination that a predetermined amount of time has passed since the at least one cache line was last accessed. The predetermined amount of time is shorter than a round-trip time to process a plurality of blocks of data stored sequentially to a ring buffer. In other embodiments, methods, systems, and computer program products are described for efficient use of cache memory using an expiration timer.

Claims

1. A method, comprising:

selectively invalidating data stored in at least one cache line of a cache memory in response to a determination that a predetermined amount of time has passed since the at least one cache line was last accessed, the predetermined amount of time being shorter than a round-trip time to process a plurality of blocks of data stored sequentially to a ring buffer.

2. The method as recited in claim 1, wherein the round-trip time is based on an amount of time required for all data blocks stored to the ring buffer to be sequentially overwritten.

3. The method as recited in claim 1, comprising:

sequentially processing first blocks of data from the plurality of blocks of data stored to the ring buffer in an order of storage to the ring buffer according to a first-in-first-out (FIFO) processing scheme; and

outputting the first blocks of data in response to processing the first blocks of data.

4. The method as recited in claim 3, comprising storing the first blocks of data to a corresponding number of cache lines in the cache memory prior to outputting the first blocks of data.

5. The method as recited in claim 1, comprising:

receiving new data to store to the ring buffer, the new data comprising one or more new bocks of data; and

overwriting a first set of blocks of data from the plurality of blocks of data stored sequentially to the ring buffer with the one or more new bocks of data, the first set of blocks equaling a number of the one or more new blocks of data,

wherein the first set of blocks of data are an oldest of the plurality of blocks of data stored sequentially to the ring buffer.

6. A system, comprising:

a processing circuit having a cache memory therein;

a ring buffer; and

logic integrated with the processing circuit, executable by the processing circuit, or integrated with and executable by the processing circuit, the logic being configured to cause the processing circuit to;

selectively invalidate data stored in at least one cache line of the cache memory in response to a determination that a predetermined amount of time has passed since the at least one cache line was last accessed, the predetermined amount of time being shorter than a round-trip time for the processing circuit to process a plurality of blocks of data stored sequentially to the ring buffer.

7. The system as recited in claim 6, wherein the round-trip time is based on an amount of time required for all data blocks stored to the ring buffer to be sequentially overwritten.

8. The system as recited in claim 6, wherein the logic is configured to cause the processing circuit to:

sequentially process first blocks of data from the plurality of blocks of data stored to the ring buffer in an order of storage to the ring buffer according to a first-in-first-out (FIFO) processing scheme; and

output the first blocks of data in response to processing the first blocks of data.

9. The system as recited in claim 8, wherein the logic is configured to cause the processing circuit to:

store the first blocks of data to a corresponding number of cache lines in the cache memory of the processing circuit prior to outputting the first blocks of data.

10. The system as recited in claim 9, wherein the logic is configured to cause the processing circuit to:

receive new data to store to the ring buffer, the new data comprising one or more new bocks of data; and

overwrite a first set of blocks of data from the plurality of blocks of data stored sequentially to the ring buffer with the one or more new bocks of data, the first set of blocks equaling a number of the one or more new blocks of data,

wherein the first set of blocks of data are an oldest of the plurality of blocks of data stored sequentially to the ring buffer.

11. A computer program product, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the embodied program instructions being executable by a processing circuit to cause the processing circuit to:

selectively invalidate, by the processing circuit, data stored in at least one cache line of a cache memory in response to a determination that a predetermined amount of time has passed since the at least one cache line was last accessed,

wherein the predetermined amount of time is shorter than a round-trip time to process a plurality of blocks of data stored sequentially to a ring buffer.

12. The computer program product as recited in claim 11, wherein the round-trip time is based on an amount of time required for all data blocks stored to the ring buffer to be sequentially overwritten.

13. The computer program product as recited in claim 11, wherein the embodied program instructions are executable by the processing circuit to cause the processing circuit to:

sequentially process, by the processing circuit, first blocks of data from the plurality of blocks of data stored to the ring buffer in an order of storage to the ring buffer according to a first-in-first-out (FIFO) processing scheme; and

output, by the processing circuit, the first blocks of data in response to processing the first blocks of data.

14. The computer program product as recited in claim 13, wherein the embodied program instructions are executable by the processing circuit to cause the processing circuit to:

store, by the processing circuit, the first blocks of data to a corresponding number of cache lines in the cache memory prior to outputting the first blocks of data.

15. The computer program product as recited in claim 14, wherein the embodied program instructions are executable by the processing circuit to cause the processing circuit to:

receive, by the processing circuit, new data to store to the ring buffer, the new data comprising one or more new bocks of data; and

overwrite, by the processing circuit, a first set of blocks of data from the plurality of blocks of data stored sequentially to the ring buffer with the one or more new bocks of data, the first set of blocks equaling a number of the one or more new blocks of data,

wherein the first set of blocks of data are an oldest of the plurality of blocks of data stored sequentially to the ring buffer.