Memory controller for flash memory with zones configured on die bounaries and with separate spare management per zone

• US 10,642,748 B1
• Filed: 08/29/2017
• Issued: 05/05/2020
• Est. Priority Date: 09/09/2014
• Status: Active Grant

• Current Assignee: Radian Memory Systems, Inc.
• Original Assignee: Radian Memory Systems, Inc.
• Inventors: Lercari, Robert, Chen, Alan, Jadon, Mike, Robertson, Craig, Kuzmin, Andrey V.
• Primary Examiner(s): Rossiter, Sean D
• Assistant Examiner(s): Wu, Stephanie
• Application Number:
  US15/690,006
• Time in Patent Office: 980 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 12/109 for multiple virtual address spaces, e.g. segmentation G06F12/1036 takes precedence
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0662 Virtualisation aspects
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.

Claims

1. A memory controller to control flash memory dies, the memory controller comprising:

a host interface to receive data storage and access requests from a host;

circuitry to receive configuration information from the host so as to define block devices, each of the block devices comprising a virtual address space mapped to a mutually-exclusive subset of the flash memory dies, wherein each of the block devices is to have a number of dies in the corresponding mutually-exclusive subset determined according to the configuration information, and wherein the corresponding virtual address space is less than an amount of storage space provided by the corresponding mutually-exclusive subset, such that the corresponding mutually-exclusive subset provides spare capacity;

circuitry to manage the spare capacity for each of the block devices on an independent basis and to intermittently reassign at least part the corresponding virtual address space in a manner that maps to the spare capacity for corresponding block device; and

circuitry to control fulfillment of the data storage and access requests from the host by issuing commands to the flash memory dies;

wherein the host is free to define the respective block devices such that the respective spare capacities are free to be different in size from one another, such that the respective virtual address spaces are configurable by the host to provide different wear characteristics;

wherein each of the data storage and access requests is to select one of the block devices; and

wherein said circuitry is to issue a first command to a flash memory die associated with a first one of the block devices, in response to a first request of the data storage and access requests from the host which selects the first one of the block devices, without awaiting completion of a second command issued by the memory controller to a flash memory die associated with a second one of the block devices, wherein the second command is issued by the memory controller in response to a second request of the data storage and access requests from the host which selects the second one of the block devices.

2. The memory controller of claim 1, wherein:

the memory controller further comprises circuitry to control the performance of maintenance operations in flash memory associated with the first one of the block devices and to control performance of maintenance operations in flash memory associated with the second one of the block devices, said maintenance operations including at least one of garbage collection or wear leveling;

the circuitry to control fulfillment of the data storage and access requests is to issue data read commands and data write commands to the flash memory associated with the first one of the block devices irrespective of whether maintenance operations are currently being performed in the second one of the block devices; and

the circuitry to control fulfillment of the data storage and access requests is to issue data read commands and data write commands to the flash memory associated with the second one of the block devices irrespective of whether maintenance operations are currently being performed in the first one of the block devices.

3. The memory controller of claim 2, wherein:

the memory controller further comprises circuitry to identify need for the maintenance operations in each of the first one of the block devices and the second one of the block devices;

the memory controller further comprises circuitry to transmit information to the host responsive to identification of the need for the maintenance operations in a given one of the first block device or the second block device, while deferring performance of the maintenance operations in the flash memory associated with the given one of the first block device or the second block device;

the circuitry to control the performance of maintenance operations in the flash memory associated with the first one of the block devices and to control performance of maintenance operations in the flash memory associated with the second one of the block devices is to initiate the maintenance operations in the given one of the first block device or the second block device responsive to a host command to proceed, received via the host interface; and

a time at which the host command to proceed is received by the memory controller at least partially dictates when performance of the maintenance operations is initiated in the flash memory associated with the given one of the first block device or the second block device by the memory controller.

4. The memory controller of claim 1, wherein:

the configuration information comprises, for each associated one of the block devices including the first one and the second one of the block devices, a respective parameterized description;

the circuitry to control fulfillment of the data storage and access requests from the host is to assign physical addresses in response to each of the data storage and access requests from the host, the physical addresses indexing storage units in which to store corresponding data; and

the assignment of the physical addresses for each of the block devices is performed in a manner dependent on the respective parameterized description for the associated one of the block devices.

5. The memory controller of claim 4, wherein:

the respective parameterized description for each associated one of the block devices identifies whether write data for sequential addresses is to be assigned to sequential physical spaces within a given one of the storage units for the associated one of the block devices or whether the write data for the sequential addresses is to be assigned to physical spaces in respective, sequential ones of the storage units for the associated one of the block devices; and

the respective parameterized description for the first one of the block devices and the respective parameterized description for the second one of the block devices can be selected to be different from one another, such that write data for sequential addresses can be assigned to physical storage space in a first manner for the first one of the block devices and write data for sequential addresses can be assigned to physical storage space in a second manner for the second one of the block devices, according to the respective parameterized description.

6. The memory controller of claim 4, wherein:

the respective parameterized description for each associated one of the block devices identifies a respective range of logical addresses that is to be linearly mapped to flash memory for the associated one of the block devices; and

a sub-address field of each of the logical addresses for each of the block devices is to be directly mapped to a structural hierarchical level for the associated one of the block devices, such that different values of the sub-address field resolve to respective ones of the storage units at the structural hierarchical level for the associated one of the block devices.

7. The memory controller of claim 4, wherein:

the respective parameterized description for each of the block devices identifies a number of the storage units at a structural hierarchical level for the associated block device that are to be reserved as spares, for selective replacement of ones of the storage units that are not reserved as spares for the associated one of the block devices; and

the configuration information for each of the block devices comprises the number for the associated block device, and the number is selectively different for each one of the block devices.

8. The memory controller of claim 1, wherein:

at least one of the flash memory dies can be programmably and selectively associated with any one of the block devices.

9. A memory controller to control flash memory dies, the memory controller comprising:

a host interface to receive data storage and access requests from a host;

circuitry to receive configuration information from the host so as to define block devices, each of the block devices comprising a virtual address space mapped to a mutually-exclusive subset of the flash memory dies, wherein each of the block devices is to have a number of dies in the corresponding mutually-exclusive subset determined according to the configuration information, and wherein the corresponding virtual address space is less than an amount of storage space provided by the corresponding mutually-exclusive subset, such that the corresponding mutually-exclusive subset provides spare capacity;

circuitry to manage the spare capacity for each of the block devices on an independent basis and to intermittently reassign at least part the corresponding virtual address space in a manner that maps to the spare capacity for corresponding block device; and

circuitry to control fulfillment of the data storage and access requests from the host by issuing commands to the flash memory dies;

wherein the host is free to define the respective block devices such that the respective spare capacities are free to be different in size from one another, such that the respective virtual address spaces are configurable by the host to provide different wear characteristics;

wherein each of the data storage and access requests is to select one of the block devices;

wherein said circuitry is to issue a first command to a flash memory die associated with a first one of the block devices in response to a first request of the data storage and access requests from the host which selects the first one of the block devices, without awaiting completion of a second command issued by the memory controller to a flash memory die associated with a second one of the block devices, wherein the second command is issued by the memory controller in response to a second request of the data storage and access requests from the host which selects the second one of the block devices; and

wherein

the memory controller further comprises circuitry to control the performance of maintenance operations in flash memory associated with the first one of the block devices and to control performance of maintenance operations in flash memory associated with the second one of the block devices, said maintenance operations including at least one of garbage collection or wear leveling,

the circuitry to control fulfillment of the data storage and access requests is to issue data read commands and data write commands to the flash memory associated with the first one of the block devices irrespective of whether maintenance operations are currently being performed in the second one of the block devices, and

the circuitry to control fulfillment of the data storage and access requests is to issue data read commands and data write commands to the flash memory associated with the second one of the block devices irrespective of whether maintenance operations are currently being performed in the first one of the block devices.

10. The memory controller of claim 9, wherein:

the memory controller further comprises circuitry to identify need for the maintenance operations in each of the first one of the block devices and the second one of the block devices;

the memory controller further comprises circuitry to transmit information to the host responsive to identification of the need for the maintenance operations in a given one of the first block device or the second block device, while deferring performance of the maintenance operations in the flash memory associated with the given one of the first block device or the second block device;

the circuitry to control the performance of maintenance operations in the flash memory associated with the first one of the block devices and to control performance of maintenance operations in the flash memory associated with the second one of the block devices is to initiate the maintenance operations in the given one of the first block device or the second block device responsive to a host command to proceed, received via the host interface; and

a time at which the host command to proceed is received by the memory controller at least partially dictates when performance of the maintenance operations is initiated in the flash memory associated with the given one of the first block device or the second block device by the memory controller.

11. The memory controller of claim 9, wherein:

the configuration information comprises, for each associated one of the block devices including the first one and the second one of the block devices, a respective parameterized description;

the circuitry to control fulfillment of the data storage and access requests from the host is to assign physical addresses in response to each of the data storage and access requests from the host, the physical addresses indexing storage units in which to store corresponding data; and

the assignment of the physical addresses for each of the block devices is performed in a manner dependent on the respective parameterized description for the associated one of the block devices.

12. The memory controller of claim 11, wherein:

the respective parameterized description for each associated one of the block devices identifies whether write data for sequential addresses is to be assigned to sequential physical spaces within a given one of the storage units for the associated one of the block devices or whether the write data for the sequential addresses is to be assigned to physical spaces in respective, sequential ones of the storage units for the associated one of the block devices; and

the respective parameterized description for the first one of the block devices and the respective parameterized description for the second one of the block devices can be selected to be different from one another, such that write data for sequential addresses can be assigned to physical storage space in a first manner for the first one of the block devices and write data for sequential addresses can be assigned to physical storage space in a second manner for the second one of the block devices, according to the respective parameterized description.

13. The memory controller of claim 11, wherein:

the respective parameterized description for each associated one of the block devices identifies a respective range of logical addresses that is to be linearly mapped to flash memory for the associated one of the block devices; and

a sub-address field of each of the logical addresses for each of the block devices is to be directly mapped to a structural hierarchical level for the associated one of the block devices, such that different values of the sub-address field resolve to respective ones of the storage units at the structural hierarchical level for the associated one of the block devices.

14. The memory controller of claim 11, wherein:

the respective parameterized description for each of the block devices identifies a number of the storage units at a structural hierarchical level for the associated block device that are to be reserved as spares, for selective replacement of ones of the storage units that are not reserved as spares for the associated one of the block devices; and

the configuration information for each of the block devices comprises the number for the associated block device, and the number is selectively different for each one of the block devices.

15. A memory controller to control flash memory dies, the memory controller comprising:

a host interface to receive data storage and access requests from a host;

circuitry to receive configuration information from the host so as to define block devices, each of the block devices comprising a virtual address spaced mapped to a mutually-exclusive subset of the flash memory dies, wherein each of the block devices is to have a number of dies in the corresponding mutually-exclusive subset determined according to the configuration information, and wherein the corresponding virtual address space is less than an amount of storage space provided by the corresponding mutually-exclusive subset, such that the corresponding mutually-exclusive subset provides spare capacity;

circuitry to manage the spare capacity for each of the block devices on an independent basis and to intermittently reassign at least part the corresponding virtual address space in a manner that maps to the spare capacity for corresponding block device; and

circuitry to control fulfillment of the data storage and access requests from the host by issuing commands to the flash memory dies;

wherein the host is free to define the respective block devices such that the respective spare capacities are free to be different in size from one another, such that the respective virtual address spaces are configurable by the host to provide different wear characteristics;

wherein each of the data storage and access requests is to select one of the block devices;

wherein said circuitry is to issue a first command to a flash memory die associated with a first one of the block devices, in response to a first request of the data storage and access requests from the host which selects the first one of the block devices, without awaiting completion of a second command issued by the memory controller to a flash memory die associated with a second one of the block devices, wherein the second command is issued by the memory controller in response to a second request of the data storage and access requests from the host which selects the second one of the block devices; and

wherein

the configuration information comprises, for each associated one of the block devices including the first one and the second one of the block devices, a respective parameterized description,

the circuitry to control fulfillment of the data storage and access requests from the host is to assign physical addresses in response to each of the data storage and access requests from the host, the physical addresses indexing storage units in which to store corresponding data, and

the assignment of the physical addresses for each of the block devices is performed in a manner dependent on the respective parameterized description for the associated one of the block devices.

16. The memory controller of claim 15, wherein:

the memory controller further comprises circuitry to control the performance of maintenance operations in flash memory associated with the first one of the block devices and to control performance of maintenance operations in flash memory associated with the second one of the block devices, said maintenance operations including at least one of garbage collection or wear leveling;

the circuitry to control fulfillment of the data storage and access requests is to issue data read commands and data write commands to the flash memory associated with the first one of the block devices irrespective of whether maintenance operations are currently being performed in the second one of the block devices; and

the circuitry to control fulfillment of the data storage and access requests is to issue data read commands and data write commands to the flash memory associated with the second one of the block devices irrespective of whether maintenance operations are currently being performed in the first one of the block devices.

17. The memory controller of claim 16, wherein:

the memory controller further comprises circuitry to identify need for the maintenance operations in each of the first one of the block devices and the second one of the block devices;

the memory controller further comprises circuitry to transmit information to the host responsive to identification of the need for the maintenance operations in a given one of the first block device or the second block device, while deferring performance of the maintenance operations in the flash memory associated with the given one of the first block device or the second block device;

the circuitry to control the performance of maintenance operations in the flash memory associated with the first one of the block devices and to control performance of maintenance operations in the flash memory associated with the second one of the block devices is to initiate the maintenance operations in the given one of the first block device or the second block device responsive to a host command to proceed, received via the host interface; and

a time at which the host command to proceed is received by the memory controller at least partially dictates when performance of the maintenance operations is initiated in the flash memory associated with the given one of the first block device or the second block device by the memory controller.

18. The memory controller of claim 15, wherein:

the respective parameterized description for each associated one of the block devices identifies whether write data for sequential addresses is to be assigned to sequential physical spaces within a given one of the storage units for the associated one of the block devices or whether the write data for the sequential addresses is to be assigned to physical spaces in respective, sequential ones of the storage units for the associated one of the block devices; and

the respective parameterized description for the first one of the block devices and the respective parameterized description for the second one of the block devices can be selected to be different from one another, such that write data for sequential addresses can be assigned to physical storage space in a first manner for the first one of the block devices and write data for sequential addresses can be assigned to physical storage space in a second manner for the second one of the block devices, according to the respective parameterized description.

19. The memory controller of claim 15, wherein:

the respective parameterized description for each associated one of the block devices identifies a respective range of logical addresses that is to be linearly mapped to flash memory for the associated one of the block devices; and

a sub-address field of each of the logical addresses for each of the block devices is to be directly mapped to a structural hierarchical level for the associated one of the block devices, such that different values of the sub-address field resolve to respective ones of the storage units at the structural hierarchical level for the associated one of the block devices.

20. The memory controller of claim 15, wherein:

the respective parameterized description for each of the block devices identifies a number of the storage units at a structural hierarchical level for the associated block device that are to be reserved as spares, for selective replacement of ones of the storage units that are not reserved as spares for the associated one of the block devices; and

the configuration information for each of the block devices comprises the number for the associated block device, and the number is selectively different for each one of the block devices.

21. The memory controller of claim 15, wherein:

at least one of the flash memory dies can be programmably and selectively associated with any one of the block devices.

22. The memory controller of claim 15, embodied as a memory controller integrated circuit, wherein each of the host and the flash memory dies are external to the memory controller integrated circuit.

23. A device, comprising:

flash memory dies; and

a memory controller to control the flash memory dies, wherein the memory controller comprises

a host interface to receive data storage and access requests from a host,

circuitry to receive configuration information from the host so as to define block devices, each of the block devices comprising a virtual address space mapped to a mutually-exclusive subset of the flash memory dies, wherein each of the block devices is to have a number of dies in the corresponding mutually-exclusive subset determined according to the configuration information, and wherein the corresponding virtual address space is less than an amount of storage space provided by the corresponding mutually-exclusive subset, such that the corresponding mutually-exclusive subset provides spare capacity,

circuitry to manage the spare capacity for each of the block devices on an independent basis and to intermittently reassign at least part the corresponding virtual address space in a manner that maps to the spare capacity for corresponding block device, and

circuitry to control fulfillment of the data storage and access requests from the host by issuing commands to the flash memory dies,

wherein the host is free to define the respective block devices such that the respective spare capacities are free to be different in size from one another, such that the respective virtual address spaces are configurable by the host to provide different wear characteristics,

wherein each of the data storage and access requests is to select one of the block devices, and

wherein said circuitry is to issue a first command to a flash memory die associated with a first one of the block devices, in response to a first request of the data storage and access requests from the host which selects the first one of the block devices, without awaiting completion of a second command issued by the memory controller to a flash memory die associated with a second one of the block devices, wherein the second command is issued by the memory controller in response to a second request of the data storage and access requests from the host which selects the second one of the block devices.

24. The device of claim 23, wherein:

the memory controller further comprises circuitry to control the performance of maintenance operations in flash memory associated with the first one of the block devices and to control performance of maintenance operations in flash memory associated with the second one of the block devices, said maintenance operations including at least one of garbage collection or wear leveling;

the circuitry to control fulfillment of the data storage and access requests is to issue data read commands and data write commands to the flash memory associated with the first one of the block devices irrespective of whether maintenance operations are currently being performed in the second one of the block devices; and

the circuitry to control fulfillment of the data storage and access requests is to issue data read commands and data write commands to the flash memory associated with the second one of the block devices irrespective of whether maintenance operations are currently being performed in the first one of the block devices.

25. The device of claim 23, wherein:

the memory controller further comprises circuitry to identify need for the maintenance operations in each of the first one of the block devices and the second one of the block devices;

the memory controller further comprises circuitry to transmit information to the host responsive to identification of the need for the maintenance operations in a given one of the first block device or the second block device, while deferring performance of the maintenance operations in the flash memory associated with the given one of the first block device or the second block device;

the circuitry to control the performance of maintenance operations in the flash memory associated with the first one of the block devices and to control performance of maintenance operations in the flash memory associated with the second one of the block devices is to initiate the maintenance operations in the given one of the first block device or the second block device responsive to a host command to proceed, received via the host interface; and

a time at which the host command to proceed is received by the memory controller at least partially dictates when performance of the maintenance operations is initiated in the flash memory associated with the given one of the first block device or the second block device by the memory controller.

26. The device of claim 23, wherein:

the configuration information comprises, for each associated one of the block devices including the first one and the second one of the block devices, a respective parameterized description;

the circuitry to control fulfillment of the data storage and access requests from the host is to assign physical addresses in response to each of the data storage and access requests from the host, the physical addresses indexing storage units in which to store corresponding data; and

the assignment of the physical addresses for each of the block devices is performed in a manner dependent on the respective parameterized description for the associated one of the block devices.