Interface from null convention logic to synchronous memory

• US 10,642,759 B2
• Filed: 04/11/2018
• Issued: 05/05/2020
• Est. Priority Date: 04/12/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Eta Compute, Inc.
• Inventors: Wijayasekara, Vidura Manu, Melton, Ben Wiley, Cope, Bryan Garnett
• Primary Examiner(s): Unelus, Ernest
• Application Number:
  US15/950,844
• Publication Number:
  US 20180300263A1
• Time in Patent Office: 755 Days
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Self-timed processing systems and methods of operating self-timed processing systems are disclosed. A self-timed processing system includes an asynchronous null convention logic (NCL) processor, a memory that accepts input signals on an active edge of a memory clock signal, and logic to combine a first acknowledge signal and a second acknowledge signal to generate the memory clock signal. The first acknowledge signal indicates input signals are ready to be accepted by the memory. The second acknowledge signal indicates data signals previously output from the memory have been accepted by the processor.

Claims

1. A self-timed processing system comprising:

an asynchronous null convention logic (NCL) processor;

a memory that accepts input signals on an active edge of a memory clock signal;

first converter circuits to convert one or more dual-rail NCL values output from the processor to single-rail input signals coupled to respective inputs of the memory;

second converter circuits to convert one or more single-rail data signals output from the memory to dual-rail values coupled to respective inputs of the processor; and

logic to combine a first acknowledge signal and a second acknowledge signal to generate the memory clock signal,

the first acknowledge signal indicating that the single-rail input signals are ready to be accepted by the memory, and

the second acknowledge signal indicating that dual-rail values based on single-rail data signals previously output from the memory have been accepted by the processor.

2. The self-timed processing system of claim 1, wherein the logic to combine the first and second acknowledge signals comprises a C element.

3. The self-timed processing system of claim 1, wherein the second converter circuits further comprise:

one or more single to dual converter (S2D) elements respectively coupled between single-rail outputs of the memory and corresponding dual-rail inputs of the processor, each S2D element configured to;

receive a single-rail signal from the memory, and

output a dual rail value to the processor, the dual-rail value alternating between a null state and a valid dual-rail conversion of the single rail signal in response to a third acknowledge signal generated by the processor.

4. The self-timed processing system of claim 3, wherein the second acknowledge signal is the third acknowledge signal.

5. The self-timed processing system of claim 3, further comprising:

a second acknowledge tree to generate the second acknowledge signal.

6. The self-timed processing system of claim 5, wherein the third acknowledge signal is individually routed from each of the one or more S2D elements to respective inputs of the second acknowledge tree.

7. The self-timed processing system of claim 5, further comprising:

respective OR gates associated with each S2D element, each OR gate having two inputs that receive the respective dual-rail value and an output that provides a respective fourth acknowledge signal indicating if the dual rail value is null or valid,

wherein the fourth acknowledge signals from the one or more S2D elements are applied to respective inputs of the second acknowledge tree.

8. The self-timed processing system of claim 1, wherein the first converter circuits further comprise:

one or more memory/acknowledge (MEMA) elements respectively coupled between dual-rail outputs of the processor and corresponding single-rail inputs of the memory, each MEMA element configured to;

receive the respective dual-rail NCL value output from the processor,

convert the dual-rail value to a single-rail signal when the respective dual-rail value is valid,

hold the single-rail signal when the respective dual-rail value changes to null, and

provide a respective fourth acknowledge signal indicating whether the respective dual rail value is valid or null.

9. The self-timed processing system of claim 8, further comprises:

a first acknowledge tree that receives the fourth acknowledge signals from the one or more MEMA elements and generates the first acknowledge signal.

10. A method for operating a processing system including an asynchronous null convention logic (NCL) processor and a synchronous memory, comprising:

converting one or more dual-rail NCL values output from the processor to single-rail input signals coupled to respective inputs of the memory;

generating a first acknowledge signal indicating that the single-rail input signals are ready to be accepted by the memory;

converting one or more single rail data signals output from the memory to dual-rail values coupled to respective inputs of the processor;

generating a second acknowledge signal indicating that dual-rail values based on single rail data signals previously output from the memory have been accepted by the processor; and

combining the first acknowledge signal and the second acknowledge signal to generate a clock signal for the memory.

11. A self-timed processing system comprising:

an asynchronous null convention logic (NCL) processor;

a synchronous memory that accepts input signals on an active edge of a memory clock signal, the input signals being based on output signals of the processor;

an output interface configured to

convert one or more dual-rail NCL values output from the processor to single-rail input signals coupled to respective inputs of the memory, and

generate a first acknowledge signal indicating that the input signals are ready to be accepted by the memory;

an input interface configured to

convert one or more single rail data signals output from the memory to dual-rail values coupled to respective inputs of the processor, and

generate a second acknowledge signal indicating that data signals previously output from the memory have been converted to dual-rail values and accepted by the processor; and

logic to combine first and second acknowledge signals to generate the memory clock signal.

12. The self-timed processing system of claim 11, wherein the logic to combine the first and second acknowledge signals comprises a C element.

13. The self-timed processing system of claim 11, wherein the output interface further comprises:

one or more memory/acknowledge (MEMA) elements respectively coupled between dual-rail outputs of the processor and corresponding single-rail inputs of the memory, each MEMA element configured to;

receive the respective dual-rail NCL value output from the processor,

convert the dual-rail value to a single-rail signal when the respective dual-rail value is valid,

hold the single-rail signal when the respective dual-rail value changes to null, and

provide a respective fourth acknowledge signal indicating whether the respective dual rail value is valid or null.

14. The self-timed processing system of claim 13, wherein the output interface further comprises:

a first acknowledge tree that receives the fourth acknowledge signals from the one or more MEMA elements and generates the first acknowledge signal.

15. The self-timed processing system of claim 11, wherein the input interface further comprises:

one or more single to dual converter (S2D) elements respectively coupled between single-rail outputs of the memory and corresponding dual-rail inputs of the processor, each S2D element configured to;

receive a single-rail signal from the memory, and

output a dual rail value to the processor, the dual-rail value alternating between a null state and a valid dual-rail conversion of the single rail signal in response to a third acknowledge signal generated by the processor.

16. The self-timed processing system of claim 15, wherein the second acknowledge signal is the third acknowledge signal.

17. The self-timed processing system of claim 15, further comprising:

a second acknowledge tree to generate the second acknowledge signal.

18. The self-timed processing system of claim 17, wherein the third acknowledge signal is individually routed from each of the one or more S2D elements to respective inputs of the second acknowledge tree.

19. The self-timed processing system of claim 17, further comprising:

respective OR gates associated with each S2D element, each OR gate having two inputs that receive the respective dual-rail value and an output that provides a respective fourth acknowledge signal indicating if the dual rail value is null or valid,

wherein the fourth acknowledge signals from the one or more S2D elements are applied to respective inputs of the second acknowledge tree.