Productivity language interface for synthesized circuits

• US 10,642,765 B1
• Filed: 11/07/2018
• Issued: 05/05/2020
• Est. Priority Date: 11/07/2018
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Lysaght, Patrick, Schelle, Graham F., Ogden, Peter K.
• Primary Examiner(s): Yimer, Getente A
• Application Number:
  US16/183,574
• Time in Patent Office: 545 Days
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405
• CPC Class Codes: G06F 2209/509 Offload
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 9/5016 the resource being the memory
• CPC Class Codes: G06F 9/5027 the resource being a machine, e.g. CPUs, Servers, Terminals

Abstract

A system includes a hardware offload circuit and a slave processor coupled to the hardware offload circuit. The system also includes a processor coupled to the slave processor and configured to execute productivity language instructions. The processor, in response to executing the productivity language instructions, is configured to generate commands and provide the commands to the slave processor. The slave processor, in executing the commands, is configured to monitor operation of the hardware offload circuit and control operation of the hardware offload circuit.

Claims

1. A system, comprising:

a hardware offload circuit implemented in programmable circuitry of a programmable integrated circuit;

a slave processor implemented within the programmable integrated circuit and coupled to the hardware offload circuit; and

a processor coupled to the slave processor and configured to execute productivity language instructions;

wherein the processor, in response to executing the productivity language instructions, is configured to generate commands and provide the commands to the slave processor;

wherein the processor is further configured to provide input data to the hardware offload circuit and receive result data from the hardware offload circuit from processing the input data; and

wherein the slave processor, in executing the commands, is configured to monitor operation of the hardware offload circuit and control operation of the hardware offload circuit by, at least in part, stopping the hardware offload circuit in response to detecting a particular operating state of the hardware offload circuit.

2. The system of claim 1, wherein the slave processor is implemented in the programmable circuitry of the programmable integrated circuit and is coupled to a sequencer of the hardware offload circuit.

3. The system of claim 1, wherein the slave processor is further configured to start the hardware offload circuit.

4. The system of claim 1, wherein the processor or the slave processor is configured to introspect a memory used by the hardware offload circuit.

5. The system of claim 4, wherein the slave processor is configured to perform the stopping the hardware offload circuit in response to detecting the particular operating state in combination with detecting a particular state of another signal from a circuit other than the hardware offload circuit.

6. The system of claim 4, wherein the processor or the slave processor is configured to compare data from the memory with expected data.

7. The system of claim 4, wherein the memory is located within the hardware offload circuit.

8. The system of claim 4, wherein the memory is an off-chip random-access memory accessible by the processor and the hardware offload circuit.

9. The system of claim 4, wherein the slave processor is configured to generate an interrupt to the processor in response to detecting the particular operating state of the hardware offload circuit.

10. The system of claim 1, wherein the slave processor comprises:

an instruction memory configured to store a binary specifying executable program code, wherein the binary is written to the instruction memory by the processor subsequent to implementation of the slave processor in programmable circuitry.

11. The system of claim 1, wherein the slave processor comprises:

an instruction memory configured to receive the commands from the processor, wherein the slave processor retrieves the commands from the instruction memory for execution; and

a data memory configured to receive the input data from the processor, wherein the slave processor is configured to retrieve the input data from the data memory and write the result data back to the data memory for retrieval by the processor.

12. A method, comprising:

generating, by a processor and in response to execution of productivity language instructions, commands;

providing the commands to a slave processor implemented within a programmable integrated circuit, wherein the slave processor is coupled to a hardware offload circuit implemented in programmable circuitry of the programmable integrated circuit;

the processor providing input data to the hardware offload circuit and receiving result data from the hardware offload circuit from processing the input data; and

controlling operation of the hardware offload circuit by the slave processor executing the commands, wherein the slave processor controls operation of the hardware offload circuit by, at least in part, stopping the hardware offload circuit in response to detecting a particular operating state of the hardware offload circuit.

13. The method of claim 12, further comprising:

implementing the slave processor within the programmable circuitry of the programmable integrated circuit.

14. The method of claim 12, further comprising:

synthesizing the hardware offload circuit and the slave processor and coupling the slave processor to a sequencer of the hardware offload circuit.

15. The method of claim 12, wherein executing selected ones of the commands causes the slave processor to generate controls signals for the hardware offload circuit, the method further comprising:

performing the stopping the hardware offload circuit using the control signals.

16. The method of claim 12, wherein executing selected ones of the commands causes the slave processor to generate controls signals for the hardware offload circuit, the method further comprising:

performing the stopping the hardware offload circuit using the control signals; and

introspecting a memory used by the hardware offload circuit.

17. The method of claim 16, further comprising:

comparing a state of data of the hardware offload circuit from the introspecting with an expected state of the data.

18. The method of claim 12, wherein executing selected ones of the commands causes the slave processor to generate controls signals for the hardware offload circuit, the method further comprising:

starting the hardware offload circuit using the control signals.

19. The method of claim 18, wherein the slave processor is configured to generate an interrupt to the processor in response to detecting the particular operating state of the hardware offload circuit.

20. The method of claim 18, wherein slave processor stops the hardware offload circuit in response to detecting the particular operating state and detecting a particular state of another signal from a circuit other than the hardware offload circuit.