Serial peripheral interface daisy chain mode system and apparatus

• US 10,642,769 B2
• Filed: 03/24/2017
• Issued: 05/05/2020
• Est. Priority Date: 03/24/2017
• Status: Active Grant

• Current Assignee: Analog Devices International Unlimited Company (Analog Devices, Inc.)
• Original Assignee: Analog Devices Global Unlimited Company (Analog Devices, Inc.)
• Inventors: Lofamia, Wes Vernon, Santillan, Jofrey, Aherne, David
• Primary Examiner(s): Lee, Chun Kuan
• Application Number:
  US15/468,781
• Publication Number:
  US 20180276157A1
• Time in Patent Office: 1,138 Days
• Field of Search: 710110
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/404 with address mapping
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247

Abstract

SPI frame for simultaneously entering 8 bit daisy-chain mode from 16 bit register addressable mode. Some products that implement SPI may be connected in a daisy chain configuration, the first slave output being connected to the second slave input, etc. The SPI port of each slave is designed to send out during the second group of clock pulses an exact copy of the data it received during the first group of clock pulses. The whole chain acts as a communication shift register; daisy chaining is often done with shift registers to provide a bank of inputs or outputs through SPI. Large latency occurs during the entry into daisy-chain mode which increases as a function of the number of linked SPI devices. A means for simultaneously instructing all connected devices to enter/enable daisy-chain mode is disclosed.

Claims

1. An apparatus for entering daisy-chain mode in an SPI device comprising:

an input to receive serial data;

a clock pin to receive a temporal signal;

a select pin; and

,

a serial output whose default instruction is a signal to enable daisy chain mode within 16 clock cycles, which is implemented at startup;

wherein, the SPI device is configured to change between daisy chain mode and a register addressable mode in response to the assertion of the select pin.

2. The apparatus of claim 1, wherein the default instruction is an SPI frame.

3. The apparatus of claim 2, wherein the SPI frame comprises a command field, an address field, and data field.

4. The apparatus of claim 2, wherein the SPI frame is 8-bits in length.

5. The apparatus of claim 1, whereby the default instruction is automatically sent after a hard reset.

6. The apparatus of claim 3, wherein said default instruction is a predetermined combination of the command field and address field.

7. The apparatus of claim 2, wherein the SPI frame is hexadecimal 0Andreas500.

8. The apparatus of claim 1, whereby the SPI device exits daisy chain mode by concurrently receiving a predetermined pattern by the clock pin and predetermined pulses by the select pin.

9. The apparatus of claim 1, whereby the SPI device exits daisy chain mode by concurrently receiving a predetermined pattern by the select pin and predetermined pulses by the clock pin.

10. The apparatus of claim 1, further comprising a pin wherein the SPI device exits daisy chain mode by receiving a binary signal thereover.

11. The apparatus of claim 1, whereby the SPI device exits daisy chain mode by power cycling.

12. A system for entering daisy-chain mode comprising:

an SPI master device; and

,

a plurality of SPI slave devices concatenated in a daisy chain configuration, each SPI slave device comprises;

an input to receive serial data;

a clock pin to receive a temporal signal;

a select pin; and

,

a serial output whose default instruction is a signal to enable daisy chain mode within 16 clock cycles, which is implemented at startup;

wherein, the SPI device is configured to change between daisy chain mode and a register addressable mode in response to concurrently receiving a predetermined pattern on the clock pin and predetermined pulses on the select pin.

13. The system of claim 12, wherein the default instruction is an SPI frame.

14. The system of claim 13, wherein the SPI frame comprises a command field, an address field, and data field.

15. The system of claim 12, wherein the SPI frame is 8-bits in length.

16. The system of claim 12, whereby the default instruction is automatically sent after a hard reset.

17. The system of claim 14, wherein said default instruction is a predetermined combination of the command field and address field.

18. The system of claim 13, wherein the SPI frame is hexadecimal 0Andreas500.

19. An apparatus for entering daisy-chain mode in an SPI device comprising:

a means for receiving serial data;

a means for receiving a clock signal;

a means for receiving a select signal; and

,

a means for transmitting serial output, wherein the default transmission is a signal to enable daisy chain mode within 16 clock cycles which is implemented at startup;

wherein, the SPI device is configured to change between daisy chain mode and a register addressable mode in response to the assertion of the means for receiving a select signal.

20. A system for entering daisy-chain mode in a plurality of serial peripheral devices within a single serial frame and dynamically change the plurality of Serial Peripheral Devices (SPD) from register addressable mode to daisy-chain mode in a single serial frame, the system comprising:

a plurality of serial peripheral devices comprising a select pin and serial device output (SDO) in a daisy chain configuration, wherein the plurality of serial peripheral devices initializes into register addressable mode after any powerup;

wherein, the serial device output default instruction is a signal to enable daisy chain mode within 16 clock cycles which is outputted to the next serial peripheral device in the system;

whereby, the serial device output default instruction is automatically clocked to the next device in the chain on the first single serial frame, after the select pin is asserted.

21. The system of claim 20, wherein the plurality of serial peripheral devices further comprises clock pin to a receive temporal signal.

22. The system of claim 21, wherein the serial device output default instruction is an SPI frame comprising 16 or fewer clock cycles pursuant to the clock pin.

23. The apparatus of claim 20, wherein the SPI single serial frame further comprises a command field, an address field, and data field.

24. The system of claim 20, whereby the serial device output default instruction is a signal is automatically sent after a hard reset.