Low-pincount high-bandwidth memory and memory bus

• US 10,642,776 B2
• Filed: 06/19/2019
• Issued: 05/05/2020
• Est. Priority Date: 06/17/2016
• Status: Active Grant

• Current Assignee: Etron Technology America Incorporated (Etron Technology Inc), Etron Technology Inc
• Original Assignee: Etron Technology Inc
• Inventors: Crisp, Richard Dewitt
• Primary Examiner(s): Abad, Farley
• Assistant Examiner(s): Yu, Henry W
• Application Number:
  US16/445,495
• Publication Number:
  US 20190303337A1
• Time in Patent Office: 321 Days
• Field of Search: 710 4- 5, 710 20- 21, 710 35, 710308
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A memory subsystem is provided, including a memory controller integrated circuit (IC), a memory bus and a memory IC, all which use fewer signals than common DDR type memory of the same peak bandwidth. Using no more than 22 switching signals, the subsystem can transfer data over 3000 Megabytes/second across the bus interconnecting the ICs. Signal count reduction is attained by time-multiplexing address/control commands onto at least some of the same signals used for data transfer. A single bus signal is used to initiate bus operation, and once in operation the single signal can transfer addressing and control information to the memory IC concurrent with data transfer via a serial protocol based on 16 bit samples of this single bus signal. Bus bandwidth can be scaled by adding additional data and data strobe IO signals. These additional data bus signals might be used only for data and data mask transport. The physical layout of one version of the memory IC dispatches switching signal terminals adjacent to one short edge of the memory die to minimize the die area overhead for controller IC memory interface circuitry when used in a stacked die multi-chip package with said memory controller IC. The memory IC interface signal placement and signal count minimize signal length and circuitry for the memory bus signals.

Claims

1. An integrated circuit (IC) primarily adapted for memory storage (Memory IC), comprising:

a plurality of sets of bus connection terminals adapted to be electrically coupled to corresponding functional terminals on a Controller IC via a collection of electrical bus conductors,

wherein a first set of the bus connection terminals of the Memory IC is configured to receive, during a command transfer time, a parallel command from the Controller IC through one or more bus conductors in a data bus group, and is further adapted to transport data between the memory IC and the controller IC using a burst mode during a data transfer time, and

wherein a second set of the bus connection terminals of the Memory IC is configured to receive, from the controller IC through a single conductor, a serial command during the data transfer time such that the serial command can direct the operation of the Memory IC by providing address and data transfer control information to the Memory IC.

2. The Memory IC of claim 1 wherein the memory IC is a Dynamic Random Access Memory (DRAM).

3. The Memory IC of claim 2 wherein the parallel command includes a fixed number of bits adapted to encode an operation code specifying at least one of the following functions:

a) a precharge function, b) an activation function, c) a refresh function, d) a mode register set function, e) a utility register write function, f) a utility register read function, g) a burst read function or h) a burst write function.

4. The Memory IC of claim 3 wherein the serial command comprises 16 bits, wherein two bits are adapted to encode the operation code.

5. The Memory IC of claim 4 wherein the operation code is adapted to specify at least one of the four following functions:

a) a null operation function, b) a burst mode function, c) an activation function or d) a utility function.

6. The Memory IC of claim 5, wherein the utility function selected by the serial command is adapted to select at least one of the following sub-commands:

a) precharge a specified bank, b) refresh a specified bank, c) burst stop, or d) toggle read/write mode, wherein the toggle read/write mode command instructs the Memory IC to switch to an opposite operating mode where burst read mode and burst write mode are defined as opposite operating modes.

7. The Memory IC of claim 2 wherein a specified bank may be precharged during burst data transfers.

8. The Memory IC of claim 2 wherein a specified row address may be activated during burst data transfers.

9. The Memory IC of claim 5, wherein the activation function selected by the serial command is adapted to specify a bank address and a row address to activate.

10. The Memory IC of claim 5 wherein the burst mode function selected by the serial command is adapted to specify a bank address and a column address from which a burst mode commences.

11. The Memory IC of claim 1 wherein a write mask is received from the data bus before data to be written into the memory is received.

12. A memory storage integrated circuit (Memory IC), configured for being interconnected to a controller IC via a bus, wherein the Memory IC is adapted to receive commands and transfer data through common connection terminals, and wherein a single connection terminal of the Memory IC, not used for transporting data during data transfer, is adapted to receive a serial command from the controller IC concurrent with the data transfer, such that the serial command can direct the operation of the Memory IC by providing address and data transfer control information to the Memory IC.

13. A memory storage integrated circuit (Memory IC), comprising:

means for receiving, during a data transfer time, a serial command from a Controller IC via a single conductor of a bus coupled to a single terminal on the Memory IC not used to transport data, the serial command directing operation of the Memory IC, by providing address and data transfer control means to the Memory IC.

14. The Memory IC of claim 13, further comprising means for receiving, during a command transfer time, a parallel command from the Controller IC.

15. The Memory IC of claim 13 wherein the serial command is a multi-bit serial command with an operation code field and an operand field, each assigned a respective bit-position range within the format of the serial command.

16. The Memory IC of claim 15 wherein the serial command'"'"'s operand field encodes a bank and column address for at least one operation code.

17. The Memory IC of claim 15 wherein the serial command'"'"'s operand field encodes a bank and row address for certain operation codes different than the operation codes of claim 15.

18. The Memory IC of claim 15 wherein one of the possible operation codes controls precharge of specified banks.

19. The Memory IC of claim 15 wherein one of the possible operation codes controls row activation within a specified bank.

20. The Memory IC of claim 15 wherein one of the possible operation codes controls column burst accesses.

21. The Memory IC of claim 15 wherein the multi-bit serial command is 16 bits long, with two bits of operation code and 14 bits of operand.