Address-based waveform database architecture

• US 10,642,811 B1
• Filed: 09/10/2014
• Issued: 05/05/2020
• Est. Priority Date: 09/10/2014
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Liddell, David K., Ng, Roger, Neema, Hem C.
• Primary Examiner(s): Pyo, Monica M
• Application Number:
  US14/482,853
• Time in Patent Office: 2,064 Days
• Field of Search: 707648, 707812, 707803, 703 13, 703 14, 717125, 326 93, 326 39
• CPC Class Codes: G06F 16/2246 Trees, e.g. B+trees
• CPC Class Codes: G06F 16/2282 Tablespace storage structures; Management thereof
• CPC Class Codes: G06F 16/289 Object oriented databases

Abstract

A waveform simulation system with a waveform database architecture satisfies different requirements of different waveform simulation tools. The waveform simulation system includes a waveform database configured to store one or more mappings that map one or more design objects to one or more memory addresses. The waveform simulation system also includes a packet processing module configured to receive simulation data from a simulation tool. The packet processing module is configured to translate the simulation data into translated simulation data that is independent of implementation details of the one or more design objects, based at least in part on the one or more mappings. In some cases, the translated simulation data may include event data stored in the waveform database.

Claims

1. A method for storing data in a waveform database, comprising:

providing a waveform database having;

a first section configured to store translated simulation data;

a second section having a table listing a plurality of design objects of a circuit design wherein for each design object, the table specifies an object type indicating a selected hardware description language of a plurality of different hardware description languages and a mapping of the design object to an address and a length of a data item for the address; and

a third section having a table specifying one of a plurality of different encodings for each object type;

electronically receiving simulation data, wherein the simulation data is a result of an executed waveform simulation process and corresponds to a change in a signal associated with a selected design object of the plurality of design objects;

translating the received simulation data using a computing device, based at least in part upon the mapping for the selected design object, into translated simulation data having a format that is independent of implementation details of the selected design object and that includes a time value, a memory address identifier corresponding to the address mapped to the selected design object from the second section, and a signal value corresponding to the change in the signal from the selected design object;

storing, using the computing device, the translated simulation data in the first section of the waveform database based upon the memory address identifier; and

subsequently presenting the translated simulation data by retrieving the translated simulation data from the first section based on requested addresses, correlating the retrieved simulation data with the type of the selected design object based on the mapping stored in the second section, and decoding the translated simulation data based on the encoding for the type of the selected design object determined from the third section.

2. The method of claim 1, wherein the selected design object is implemented using a first type of encoding, and at least one other design object of the circuit design is implemented using a second type of encoding that is different from the first type.

3. The method of claim 1, wherein the translating the received simulation data determines the memory address identifier based at least in part upon a hardware description language in which the selected design object is implemented.

4. The method of claim 1, wherein the translated simulation data are stored in one of a plurality of buckets based on the memory address identifier, wherein each of the plurality of buckets corresponds to an address range such that each bucket stores translated simulation data for each of the plurality of design objects mapped to a memory address in the address range of the respective bucket.

5. The method of claim 1, wherein the waveform database further comprises:

a fourth section configured to instruct a waveform viewer to load a specific set of signals.

6. The method of claim 1, wherein:

the mapping maps the selected design object to two or more memory addresses; and

the translated simulation data is associated with the two or more memory addresses.

7. The method of claim 1, wherein an implementation detail of the selected design object comprises a hardware description language of the selected design object, and wherein a format of the translated simulation data is independent of the hardware description language of the selected design object.

8. A method of retrieving data from a waveform database, comprising:

storing, using a computing device, translated simulation data for a plurality of design objects of a circuit design in a first section of the waveform database, wherein the first section is separate from a second section of the waveform database configured to store a mapping and a third section of the waveform database configured to store a data type;

wherein the translated simulation data is generated by translating, based at least in part upon the mapping, received simulation data for an executed waveform simulation process corresponding to changes in signals associated with the plurality of design objects into time values, memory address identifiers, and signal values corresponding to the changes in the signals from the plurality of design objects;

electronically receiving a request from a waveform viewer for a waveform of the simulation data;

identifying one or more memory addresses in a memory corresponding to the requested waveform based at least in part on the mapping that maps the plurality of design objects to the one or more memory addresses, wherein the memory address identifiers correspond to the one or more memory addresses;

determining one or more event data based on the one or more identified memory addresses by electronically accessing the one or more event data from the first section of the waveform database;

processing the one or more event data for presentation based on a selected design object of the plurality of design objects and the data type for the one or more event data determined from the third section of the waveform database using the mapping; and

wherein the translated simulation data are stored in one of a plurality of buckets based on the memory address identifiers, wherein each of the plurality of buckets corresponds to an address range such that each bucket stores translated simulation data for each of the plurality of design objects mapped to a memory address in the address range of the respective bucket.

9. The method of claim 8, wherein the processing the one or more event data comprises, in response to electronically accessing the one or more event data from the waveform database, first creating one or more B-trees using the one or more event data prior to sending the one or more event data to the waveform viewer.

10. The method of claim 8, wherein the processing the one or more event data comprises, in response to electronically accessing the one or more event data from the waveform database, creating memory images for certain respective times specified in the accessed one or more event data.

11. The method of claim 8, wherein the identifying the one or more memory addresses is also based at least in part upon a type of data encoding used to implement the selected design object.

12. A waveform simulation system, comprising:

computer hardware configured to initiate operations including;

providing a waveform database having;

a first section configured to store translated simulation data;

a second section having a table listing a plurality of design objects of a circuit design wherein for each design object, the table specifies an object type indicating a selected hardware description language of a plurality of different hardware description languages and a mapping of the design object to an address and a length of a data item for the address; and

a third section having a table specifying one of a plurality of different encodings for each object type;

electronically receiving simulation data, wherein the simulation data is a result of an executed waveform simulation process and corresponds to a change in a signal associated with a selected design object of the plurality of design objects;

translating the received simulation data, based at least in part upon the mapping for the selected design object, into translated simulation data having a format that is independent of implementation details of the selected design object and that includes a time value, a memory address identifier corresponding to the address mapped to the selected design object from the second section, and a signal value corresponding to a change in the signal from the selected design object;

storing the translated simulation data in the first section of the waveform database based upon the memory address identifier; and

subsequently presenting the translated simulation data by retrieving the translated simulation data from the first section based on requested addresses, correlating the retrieved simulation data with the type of the selected design object based on the mapping stored in the second section, and decoding the translated simulation data based on the encoding for the type of the selected design object determined from the third section.

13. The system of claim 12, wherein the selected design object is implemented using a first type of encoding, and at least one other design object of the circuit design is implemented using a second type of encoding that is different from the first type.

14. The system of claim 12, wherein the translating determines the address identifier based at least in part on a hardware description language in which the selected design object is implemented.

15. The system of claim 12, wherein the translated simulation data are stored in one of a plurality of buckets based on the memory address identifier, wherein each of the plurality of buckets corresponds to an address range such that each bucket stores translated simulation data for each of the plurality of design objects mapped to a memory address in the address range of the respective bucket.

16. The system of claim 12, wherein the waveform database further comprises:

a fourth section configured to instruct a waveform viewer to load a specific set of signals.

17. The system of claim 12, wherein:

the mapping maps the selected design object to two or more memory addresses; and

the translated simulation data is associated with the two or more memory addresses.

18. The system of claim 12, wherein the waveform database is also configured to store streaming information that includes host-specific data.

19. The system of claim 12, wherein the waveform database is also configured to store information indicating how waveform data are to be packaged for presentation.