Modular periphery tile for integrated circuit device
First Claim
Patent Images
1. An integrated circuit system, comprising:
- a first die comprising first programmable fabric circuitry; and
a second die comprising a first modular periphery intellectual property (IP) tile, wherein the first modular periphery IP tile comprises first circuitry configurable to perform a first function in association with the first programmable fabric circuitry, wherein the second die is communicatively coupled to the first die via a modular interface that is configurable to enable communication;
between the first die and the second die, when the first die is coupled to the second die via the modular interface;
between the first die and a third die, when the first die is coupled to the third die via the modular interface instead of the second die, wherein the third die comprises a second modular periphery intellectual property (IP) tile, wherein the second modular periphery IP tile comprises second circuitry configured to perform a second function in association with the first programmable fabric circuitry; and
between the second die and a fourth die, when the second die is coupled to the fourth die via the modular interface instead of the first die, wherein the fourth die comprises second programmable fabric circuitry, and wherein the first circuitry of the first modular periphery IP tile is configured to perform the first function in association with the second programmable fabric circuitry.
2 Assignments
0 Petitions
Accused Products
Abstract
Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.
4 Citations
17 Claims
-
1. An integrated circuit system, comprising:
-
a first die comprising first programmable fabric circuitry; and a second die comprising a first modular periphery intellectual property (IP) tile, wherein the first modular periphery IP tile comprises first circuitry configurable to perform a first function in association with the first programmable fabric circuitry, wherein the second die is communicatively coupled to the first die via a modular interface that is configurable to enable communication; between the first die and the second die, when the first die is coupled to the second die via the modular interface; between the first die and a third die, when the first die is coupled to the third die via the modular interface instead of the second die, wherein the third die comprises a second modular periphery intellectual property (IP) tile, wherein the second modular periphery IP tile comprises second circuitry configured to perform a second function in association with the first programmable fabric circuitry; and between the second die and a fourth die, when the second die is coupled to the fourth die via the modular interface instead of the first die, wherein the fourth die comprises second programmable fabric circuitry, and wherein the first circuitry of the first modular periphery IP tile is configured to perform the first function in association with the second programmable fabric circuitry. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
-
12. An integrated circuit system, comprising:
-
a programmable fabric die comprising; a first fabric network-on-chip (FNOC) configured to facilitate high-bandwidth communication, wherein the first FNOC comprises a network-on-chip (NOC) embedded within the programmable fabric die; and a first direct interface column configured to facilitate direct communication without interfacing via the first FNOC, wherein the first direct interface column comprises a time division multiplexing (TDM) interface; a modularized periphery intellectual property (IP) tile communicatively coupled to the programmable fabric die, wherein the modularized periphery IP tile comprises; a second FNOC configured to facilitate high-bandwidth communication with the programmable fabric die by interfacing with second FNOC; and a second direct interface column configured to facilitate direct communication with the programmable fabric die by interfacing with the first direct interface column without interfacing via the second FNOC, wherein the second direct interface column comprises the TDM interface. - View Dependent Claims (13, 14, 15, 16, 17)
-
Specification