Verifying planarization performance using electrical measures
First Claim
1. A computer-implemented method for verifying planarization performance using electrical measures, the computer-implemented method comprising:
- modeling, using a processor, a planarization layer for a topography of a device;
designing a chip including one or more structures of a design;
measuring electrical characteristics of the one or more structures, wherein the electrical characteristics include a threshold voltage of each of the one or more structures;
receiving target specification for the one or more structures;
comparing measured electrical characteristics of the one or more structures to the target specifications for the one or more structures;
applying the planarization model to the one or more structures;
correlating the measured electrical characteristics to the planarization model; and
modifying a process for fabricating the chip based at least in part on a result of the correlation.
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Accused Products
Abstract
Embodiments of the invention include techniques for verifying planarization performance using electrical measures, the techniques include modeling, by a processor, a planarization layer for a topography of a device, and designing a chip including one or more structures. The techniques also include measuring electrical characteristics of the one or more structures, and comparing measured electrical characteristics of the one or more structures to target specifications for the one or more structures. Techniques include applying the planarization model to the one or more structures, and correlating the measured electrical characteristics to the planarization layer.
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Citations
16 Claims
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1. A computer-implemented method for verifying planarization performance using electrical measures, the computer-implemented method comprising:
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modeling, using a processor, a planarization layer for a topography of a device; designing a chip including one or more structures of a design; measuring electrical characteristics of the one or more structures, wherein the electrical characteristics include a threshold voltage of each of the one or more structures; receiving target specification for the one or more structures; comparing measured electrical characteristics of the one or more structures to the target specifications for the one or more structures; applying the planarization model to the one or more structures; correlating the measured electrical characteristics to the planarization model; and modifying a process for fabricating the chip based at least in part on a result of the correlation. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A system for verifying planarization performance using electrical measures, the system comprising:
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storage medium, the storage medium being communicatively coupled to a processor; the processor configured to; model a planarization layer for a topography of a device; design a chip including one or more structures; collect measured electrical characteristics of the one or more structures wherein the electrical characteristics include a threshold voltage of each of the one or more structures; compare measured electrical characteristics of the one or more structures to target specifications for the one or more structures; apply the planarization model to the one or more structures; correlate the measured electrical characteristics to the planarization layer; and modify a process for fabricating the chip based at least in part on a result of the correlation. - View Dependent Claims (9, 10, 11, 12)
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13. A computer program product for verifying planarization performance using electrical measurements, the computer program product comprising:
a computer readable storage medium having stored thereon program instructions executable by a processor to cause the processor to; model a planarization layer for a topography of a device; design a chip including one or more structures; collect measured electrical characteristics of the one or more structures wherein the electrical characteristics include a threshold voltage of each of the one or more structures; compare measured electrical characteristics of the one or more structures to target specifications for the one or more structures; apply the planarization model to the one or more structures; correlate the measured electrical characteristics to the planarization layer; and modify a process for fabricating the chip based at least in part on a result of the correlation. - View Dependent Claims (14, 15, 16)
Specification