Automatic design and verification of safety critical electronic systems

• US 10,643,011 B1
• Filed: 06/29/2018
• Issued: 05/05/2020
• Est. Priority Date: 06/29/2018
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Nardi, Alessandra, Armato, Antonino
• Primary Examiner(s): Alam, Mohammed
• Application Number:
  US16/023,937
• Time in Patent Office: 676 Days
• Field of Search: 716102
• CPC Class Codes: G06F 2111/04 Constraint-based CAD
• CPC Class Codes: G06F 2111/20 Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules
• CPC Class Codes: G06F 2115/08 Intellectual property [IP] blocks or IP cores
• CPC Class Codes: G06F 2119/02 Reliability analysis or reliability optimisation; Failure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]
• CPC Class Codes: G06F 30/15 Vehicle, aircraft or watercraft design
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/3308 using simulation
• CPC Class Codes: G06F 30/3323 using formal methods, e.g. equivalence checking or property checking
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

Devices, methods, computer readable media, and other embodiments are described for design and verification of safety critical electronic systems. Some embodiments integrate functional safety (FS) data with circuit design data for use in electronic design automation (EDA) operations. One embodiment involves a device accessing FS and circuit design data; automatically analyzing register transfer level (RTL) design data using the FS data to perform one or more FS quality checks; and placing and routing the circuit design using the RTL design data and the set of FS data to perform FS-aware placement and routing. In some embodiments, failure modes and associated safety mechanisms to improve safety metrics associated with failure modes are automatically added to the circuit design during EDA operations. In other embodiments, additional FS-aware operations are performed. In some embodiments, the FS data is structured as a single Unified Safety Format (USF) file.

Claims

1. A method of electronic design automation (EDA) to generate a circuit design meeting functional safety (FS) design criteria, the method comprising:

accessing, using one or more hardware processors, register transfer level (RTL) design data for the circuit design stored in memory, the circuit design comprising a plurality of circuit objects;

accessing, using the one or more hardware processors, a set of FS data associated with an initial circuit design, the set of FS data describing one or more failure modes associated with the plurality of circuit objects, failure rate information for the plurality of circuit objects, and an associated FS design criterion for each failure mode;

automatically analyzing the RTL design data using the set of FS data to perform one or more FS quality checks; and

placing and routing the circuit design using the RTL design data and the set of FS data to perform FS-aware placement and routing, wherein the circuit design is provided for generating semiconductor circuits.

2. The method of claim 1, further comprising:

automatically adjusting the RTL design data to implement a FS design adjustment when a FS quality check fails to meet the associated FS design criteria; and

storing a circuit design file comprising FS-aware placement and routing data.

3. The method of claim 1, wherein the set of FS data comprises a single Unified Safety Format (USF) file.

4. The method of claim 3, wherein the set FS data of the USF file further comprises:

safety intent data comprising one or more part or sub-part fields and one or more failure mode fields;

failure mode design mapping data comprising failure mode distribution fields, instance target fields, and observation point fields; and

safety design data comprising safety mechanism fields each identifying one or more safety mechanisms.

5. The method of claim 4, wherein the FS data of the USF file further comprises:

safety mechanism design mapping data comprising diagnostic coverage fields, safety mechanism instant target fields, and detection port fields; and

safety metric data comprising fault metric fields;

wherein each field of the USF file is associated with a corresponding circuit object of the plurality of circuit objects.

6. The method of claim 5, wherein fields of the USF file associated with corresponding circuit objects of the plurality of circuit objects of the RTL design data are mapped during synthesis operations to generate a gate-level netlist.

7. The method of claim 6, further comprising:

performing equivalence checking of the RTL design data and the gate-level netlist using the FS data following synthesis of the gate-level netlist.

8. The method of claim 1, wherein automatically analyzing the RTL design data using the set of FS data comprises determining that safety metric data of the FS data for the circuit design does not meet a safety threshold.

9. The method of claim 8, further comprising:

identifying a safety mechanism associated with the safety metric data of the FS data for the circuit design that does not meet the safety threshold; and

automatically updating the circuit design using the safety mechanism to improve the safety metric data.

10. The method of claim 9, wherein the safety mechanism comprises addition of modular redundancy circuitry for a circuit object of the plurality of circuit objects.

11. The method of claim 9, wherein the safety mechanism comprises addition of parity check circuitry for one or more registers of the plurality of circuit objects.

12. The method of claim 9, further comprising performing fault injection operations to validate diagnostic coverage of safety mechanisms described by the set of FS data.

13. The method of claim 9, further comprising generating one or more FS reports using the FS data, the FS reports comprising first failure mode, effects, and diagnostic analysis (FMEDA) data connecting the circuit design with the FS data and dependent failure analysis (DFA) reporting describing DFA countermeasures incorporated in the circuit design.

14. The method of claim 9, further comprising performing FS-aware signoff of the circuit design following placement and routing to identify and verify safety layout constraint implemented for safety mechanisms in the circuit design.

15. An electronic design automation (EDA) device for generating a circuit design meeting functional safety (FS) design criteria, the EDA device comprising:

a memory configured to store;

register transfer level (RTL) design data for the circuit design stored in memory, the circuit design comprising a plurality of circuit objects;

FS data associated and the circuit design, the FS data comprising safety intent data for one or more of the plurality of circuit objects, failure rate information for the plurality of circuit objects, and associated failure mode design mapping, safety mechanism design mapping, safety design, and safety metric data for each of the one or more circuit objects described by the FS data; and

a file describing one or more failure modes associated with a plurality of design objects and associated FS design criteria for each failure mode; and

one or more processors coupled to the memory and configured to;

automatically analyze the RTL design data using the FS for one or more unmet FS design criteria to identify one or more safety mechanisms associated with one or more failure modes;

update the circuit design with safety mechanism circuit objects associated with the one or more safety mechanisms to generate an updated circuit design;

synthesize the updated circuit design using the FS data and the one or more FS design criteria; and

place and route the updated circuit design using the FS data to perform FS-aware placement and routing, wherein the updated circuit design is provided for generating semiconductor circuits.

16. The EDA device of claim 15 wherein the one or more processors are further configured to:

identify a safety mechanism associated with the safety metric data of the FS data for the circuit design that does not meet a safety threshold, wherein automatically analyzing the RTL design data using the FS data comprises determining that safety metric data of the FS data for the circuit design does not meet a safety threshold; and

automatically update the circuit design using the safety mechanism to improve the safety metric data, wherein the safety mechanism comprises addition of modular redundancy circuitry for a circuit object of the plurality of circuit objects.

17. The EDA device of claim 15, wherein the FS data comprises a single Unified Safety Format (USF) file, and wherein the FS data of the USF file further comprises:

safety intent data comprising one or more part or sub-part fields and one or more failure mode fields;

failure mode design mapping data comprising failure mode distribution fields, instance target fields, and observation point fields; and

safety design data comprising safety mechanism fields each identifying one or more safety mechanisms.

18. A non-transitory computer readable storage medium comprising instructions that, when executed by one or more processors of a device, cause the device to perform operations for electronic design automation (EDA) to generate a circuit design meeting functional safety (FS) design criteria, the operations comprising:

accessing, using one or more hardware processors, register transfer level (RTL) design data for the circuit design stored in memory, the circuit design comprising a plurality of circuit objects;

accessing, using the one or more hardware processors, a Unified Safety Format (USF) file associated with the FS design criteria and the circuit design, the USF file describing one or more failure modes associated with the plurality of design objects, failure rate information for the plurality of circuit objects, and associated FS design criteria for each failure mode;

automatically analyzing the RTL design data using the USF file for one or more FS design criteria quality checks to identify one or more safety mechanisms associated with one or more failure modes;

updating the circuit design with safety mechanism objects associated with the one or more safety mechanisms to generate an updated circuit design;

synthesizing a gate-level netlist based on the updated circuit design, the USF file, and the one or more FS design criteria;

automatically performing FS-aware verification and checking of the updated circuit design;

generating one or more sets of FS reporting data using the gate-level netlist, the FS-aware verification and checking of the updated circuit design, and the FS data;

placing and routing the updated circuit design using the FS data to perform FS-aware placement and routing; and

generating an output circuit design file with placing and routing data for the updated circuit design, wherein the output circuit design file is provided for generating semiconductor circuits.

19. The non-transitory computer readable medium of claim 18, wherein the set of FS data comprises a single Unified Safety Format (USF) file, and wherein the set FS data of the USF file further comprises:

safety intent data comprising one or more part or sub-part fields and one or more failure mode fields;

failure mode design mapping data comprising failure mode distribution fields, instance target fields, and observation point fields; and

safety design data comprising safety mechanism fields each identifying one or more safety mechanisms;

safety mechanism design mapping data comprising diagnostic coverage fields, safety mechanism instant target fields, and detection port fields; and

safety metric data comprising fault metric fields;

wherein each field of the USF file is associated with a corresponding circuit object of the plurality of circuit objects; and

wherein fields of the USF file associated with corresponding circuit objects of the plurality of circuit objects of the RTL design data are mapped during synthesis operations to generate a gate-level netlist.

20. The non-transitory computer readable medium of claim 18, wherein the instructions further cause the device to perform operations comprising:

generating first failure mode, effects, and diagnostic analysis (FMEDA) report data using the RTL design data and the USF file prior to placing and routing the circuit design;

further synthesizing the gate-level netlist based on an equivalence check for the RTL design data; and

generating second FMEDA report data from the gate-level netlist and the USF file as part of a FS verification.