System and method to estimate a number of layers needed for routing a multi-die package
First Claim
1. A computer implemented method for implementing an IC package design with an IC package design estimator, comprising:
- estimating, using at least one processor, a number of layers for an integrated circuit (IC) package design that includes a plurality of IC die designs;
determining whether the estimated number of layers can accommodate routing demands for interconnections between the IC package design and each of the plurality of IC die designs;
identifying a number of layers required to perform routing between each of the plurality of IC die designs;
combining the plurality of IC die designs into a single die design;
determining a power layer or ground layer based upon, at least in part, one or more factors; and
generating an output for the IC package design based upon, at least in part, the estimated number of layers and the power layer or ground layer.
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Abstract
Embodiments included herein are directed towards a system and method for implementing an IC package design with an IC package design estimator. Embodiments may include estimating a number of layers for an integrated circuit (IC) package design that includes a plurality of IC die designs. Embodiments may further include determining whether the estimated number of layers can accommodate routing demands for interconnections between the IC package design and each of the plurality of IC die designs. Embodiments may also include identifying a number of layers required to perform routing between each of the plurality of IC die designs. Embodiments may further include determining a power layer or ground layer based upon, at least in part, one or more factors and generating an output for the IC package design based upon, at least in part, the estimated number of layers and the power layer or ground layer.
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Citations
20 Claims
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1. A computer implemented method for implementing an IC package design with an IC package design estimator, comprising:
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estimating, using at least one processor, a number of layers for an integrated circuit (IC) package design that includes a plurality of IC die designs; determining whether the estimated number of layers can accommodate routing demands for interconnections between the IC package design and each of the plurality of IC die designs; identifying a number of layers required to perform routing between each of the plurality of IC die designs; combining the plurality of IC die designs into a single die design; determining a power layer or ground layer based upon, at least in part, one or more factors; and generating an output for the IC package design based upon, at least in part, the estimated number of layers and the power layer or ground layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A system for implementing an IC package design with an IC package design estimator, comprising:
at least one processor configured to estimate a number of layers for an integrated circuit (IC) package design that includes a plurality of IC die designs, the at least one processor further configured to determine whether the estimated number of layers can accommodate routing demands for interconnections between the IC package design and each of the plurality of IC die designs, the at least one processor further configured to identify a number of layers required to perform routing between each of the plurality of IC die designs, the at least one processor further configured to combine the plurality of IC die designs into a single die design, the at least one processor further configured to determine a power layer or ground layer based upon, at least in part, one or more factors and to generate an output for the IC package design based upon, at least in part, the estimated number of layers and the power layer or ground layer. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. A non-transitory computer readable storage medium having stored thereon instructions, which when executed by a processor result in one or more operations, the operations comprising:
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estimating, using at least one processor, a number of layers for an integrated circuit (IC) package design that includes a plurality of IC die designs; determining whether the estimated number of layers can accommodate routing demands for interconnections between the IC package design and each of the plurality of IC die designs; identifying a number of layers required to perform routing between each of the plurality of IC die designs; combining the plurality of IC die designs into a single die design; determining a power layer or ground layer based upon, at least in part, one or more factors; and generating an output for the IC package design based upon, at least in part, the estimated number of layers and the power layer or ground layer. - View Dependent Claims (20)
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Specification