Differential non-volatile memory cell for artificial neural network
First Claim
1. An apparatus, comprising:
- an array of non-volatile memory cells, including a first bit line, a plurality of word line pairs and a plurality of non-volatile memory cell pairs, each word line of a word line pair being connected to the first bit line by one of the memory cells of a corresponding memory cell pair;
one or more control circuits connected to the array of non-volatile memory cells, the one or more control circuits configured to;
receive one or more binary inputs;
apply one or more voltage patterns, each corresponding to one of the binary inputs, to a corresponding one or more selected word line pairs of the plurality of word line pairs, a first value of the binary input corresponding to a high voltage level on a first of the selected word line pair and a low voltage level a second of the word line pair and a second value of the binary input corresponding to the low voltage level on the first of the selected word line pair and the high voltage level the second of the word line pair; and
determine a voltage level on the first bit line in response to applying the one or more voltage patterns the corresponding one or more selected word line pairs.
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Abstract
Use of a non-volatile memory array architecture to realize a neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a neural network is formed by a differential memory cell of two individual memory cells, such as a memory cells having a programmable resistance, each connected between a corresponding one of a word line pair and a shared bit line. An input is applied as a pattern of voltage values on word line pairs connected to the unit synapses to perform the multiplication of the input with the weight by determining a voltage level on the shared bit line. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a summation circuit.
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Citations
20 Claims
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1. An apparatus, comprising:
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an array of non-volatile memory cells, including a first bit line, a plurality of word line pairs and a plurality of non-volatile memory cell pairs, each word line of a word line pair being connected to the first bit line by one of the memory cells of a corresponding memory cell pair; one or more control circuits connected to the array of non-volatile memory cells, the one or more control circuits configured to; receive one or more binary inputs; apply one or more voltage patterns, each corresponding to one of the binary inputs, to a corresponding one or more selected word line pairs of the plurality of word line pairs, a first value of the binary input corresponding to a high voltage level on a first of the selected word line pair and a low voltage level a second of the word line pair and a second value of the binary input corresponding to the low voltage level on the first of the selected word line pair and the high voltage level the second of the word line pair; and determine a voltage level on the first bit line in response to applying the one or more voltage patterns the corresponding one or more selected word line pairs. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method, comprising:
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receiving a plurality of input values; translating each of the plurality of input values into a corresponding first voltage pattern, each first voltage pattern being one of a plurality of voltage patterns comprising a pair of voltage values; applying the plurality of first voltage patterns to one or more pairs of word lines each connected through a first corresponding pair of non-volatile memory cells to a first shared bit line, wherein no more than one first voltage pattern is applied to any single pair of word lines at a time; and determining one or more voltage levels on the first shared bit line in response to applying the plurality of first voltage patterns to the one or more pairs of word lines. - View Dependent Claims (15, 16, 17)
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18. A non-volatile memory circuit, comprising:
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an array of a plurality of non-volatile memory cells connected between one of a plurality of word lines and one of a plurality of bit lines, the non-volatile memory cells configured to store weights of a neural network with each weight stored in a pair of the non-volatile memory cells, each of the memory cells of each pair connected between a distinct one of a pair of word lines and a shared bit line; and one or more control circuits connected to the array of non-volatile memory cells, the one or more control circuits configured to; receive one or more inputs for a layer of a neural network and convert the one or more inputs into a corresponding one of a set of voltage patterns; apply the one or more voltage patterns to word lines of the array of non-volatile memory cells to thereby perform an in-array multiplication of the one or more inputs with the weights; and accumulate results of the in-array multiplication. - View Dependent Claims (19, 20)
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Specification