Display device with inspection transistor and method for inspecting display device

• US 10,643,514 B2
• Filed: 08/08/2018
• Issued: 05/05/2020
• Est. Priority Date: 02/29/2016
• Status: Active Grant

• Current Assignee: Panasonic Intellectual Property Corporation of America (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Liquid Crystal Display Company Limited (Panasonic Holdings Corporation)
• Inventors: Goto, Hiroaki, Hirata, Masafumi
• Primary Examiner(s): Park, Sanghyuk
• Application Number:
  US16/058,557
• Publication Number:
  US 20180350285A1
• Time in Patent Office: 636 Days
• CPC Class Codes: G02F 1/1309 Repairing; Testing
• CPC Class Codes: G02F 1/136254 Checking; Testing
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G09G 2310/0267 Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
• CPC Class Codes: G09G 2330/12 Test circuits or failure detection circuits included in a display system, as permanent part thereof
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/36 using liquid crystals
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors

Abstract

A display device comprises: inspection transistors electrically connected to signal lines respectively; an inspection wiring through which an inspection signal is supplied to the inspection transistors; and an abnormality determination unit that determines whether the display panel is abnormal. The signal line is electrically connected to a gate electrode of the inspection transistor, and the abnormality determination unit determines whether the display panel is abnormal based on a voltage level of the inspection signal outputted from a source electrode of the inspection transistor.

Claims

1. A display device comprising:

a plurality of signal lines arranged in a display region of a display panel;

a plurality of inspection transistors each of which has a drain electrodes, a source electrode and a gate electrode electrically connected to a corresponding one of the plurality of signal lines;

an inspection wiring through which an inspection signal is supplied to the drain electrodes of the plurality of inspection transistors, the inspection wiring including a first inspection wiring and a second inspection wiring; and

an abnormality determination unit that are electrically connected to at least one of the source electrodes of the plurality of inspection transistors and determines whether the display panel is abnormal,

wherein the abnormality determination unit determines whether the display panel is abnormal based on a voltage level of the inspection signal outputted from the at least one of the source electrodes of the plurality of inspection transistors,

the plurality of signal lines are divided into at least a first group including a part of the plurality of signal lines immediately adjacent to each other and a second group including a part of the plurality of signal lines immediately adjacent to each other,

a part of the plurality of inspection transistors have control electrodes respectively and electrically connected to the plurality of signal lines included in the first group, are connected in cascade, and are electrically connected to the first inspection wiring, and

another part of the plurality of inspection transistors have control electrodes respectively and electrically connected to the plurality of signal lines included in the second group, are connected in cascade, and are electrically connected to the second inspection wiring.

2. The display device according to claim 1, wherein

the plurality of signal lines are a plurality of data lines through which image data is supplied to each pixel,

in each of two inspection transistors immediately adjacent to each other in the first group, respective gate electrodes are electrically connected to different data lines, and the source electrode of one of the inspection transistors and the drain electrode of the other inspection transistor are electrically connected to each other, and

in each of two inspection transistors immediately adjacent to each other in the second group, respective gate electrodes are electrically connected to different data lines, and the source electrode of one of the inspection transistors and the drain electrode of the other inspection transistor are electrically connected to each other.

3. The display device according to claim 1, wherein

the plurality of signal lines are a plurality of gate lines through which a gate signal is supplied to a transistor of each pixel.

4. A display device comprising:

a plurality of gate lines arranged in a display area of a display panel;

a plurality of first inspection transistors, each of which has a drain electrode, a source electrode and a gate electrode electrically connected to a corresponding one of the plurality of gate lines;

a plurality of second inspection transistors, each of which has a drain electrode, a source electrode and a gate electrode electrically connected to a corresponding one of the source electrodes of the plurality of first inspection transistors;

a plurality of capacitors, each of which has a first electrode electrically connected to a corresponding one of the source electrodes of the plurality of first inspection transistors and a corresponding one of the gate electrodes of the plurality of second inspection transistors;

an inspection wiring through which an inspection signal is supplied to the drain electrodes of the plurality of first inspection transistors and the drain electrodes of the plurality of second inspection transistors; and

an abnormality determination unit electrically connected to at least one of the source electrodes of the plurality of second inspection transistors and that determines whether the display panel is abnormal, wherein

the abnormality determination unit determines whether the display panel is abnormal based on a voltage level of the inspection signal outputted from the at least one of the source electrodes of the plurality of second inspection transistors.

5. The display device according to claim 4, further comprising a reset line electrically connected to second electrodes of the plurality of capacitors, a reset signal being supplied through the reset line in order to discharge the plurality of capacitors.

6. A method for inspecting a display device,

the display device including:

a plurality of gate lines arranged in a display area of the display panel;

a plurality of first inspection transistors each of which has a drain electrode, a source electrode and a gate electrode electrically connected to a corresponding one of the plurality of gate lines;

a plurality of second inspection transistors each of which has a drain electrode, a source electrode and a gate electrode electrically connected to a corresponding one of the source electrodes of the plurality of first inspection transistors;

a plurality of capacitors each of which has a first electrode electrically connected to a corresponding one of the source electrodes of the plurality of first inspection transistors and a corresponding one of the gate electrodes of the plurality of second inspection transistors; and

an inspection wiring through which an inspection signal is supplied to the drain electrodes of the plurality of first inspection transistors and the drain electrodes of the plurality of second inspection transistors,

the method comprising the steps of;

supplying sequentially a gate signal to the plurality of gate lines in a writing period and supplying the inspection signal having a voltage level bringing the plurality of second inspection transistors into an on state to the drain electrodes of the plurality of first inspection transistors through the inspection wiring in the writing period;

supplying the inspection signal to the drain electrodes of the plurality of second inspection transistors through the inspection wiring in a vertical flyback period; and

determining whether the display panel is abnormal based on a voltage level of the inspection signal outputted from at least one of the source electrode of the second inspection transistor.

7. The method according to claim 6, further comprising the step of supplying a reset signal to second electrodes of the capacitors through a reset line after determining whether the display panel is abnormal in the vertical flyback period.