Data line demultiplexer, display substrate, display panel and display device

• US 10,643,516 B2
• Filed: 06/23/2017
• Issued: 05/05/2020
• Est. Priority Date: 11/15/2016
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd.
• Original Assignee: BOE Technology Group Co., Ltd.
• Inventors: Cheng, Hongfei, Li, Pan
• Primary Examiner(s): Eurice, Michael J
• Application Number:
  US15/745,163
• Publication Number:
  US 20190012947A1
• Time in Patent Office: 1,047 Days
• CPC Class Codes: G09F 9/00 Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the variable information is permanently attached to a movable support G09F11/00; abacus G06C1/00; slide-rules G06G1/00
• CPC Class Codes: G09G 2300/0823 used to establish symmetry in driving, e.g. with polarity inversion
• CPC Class Codes: G09G 2310/0235 Field-sequential colour display
• CPC Class Codes: G09G 2310/0297 Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/2003 Display of colours specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 3/3275 Details of drivers for data electrodes
• CPC Class Codes: G09G 3/3607 for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels display of colours in flat matrix panels other than liquid crystal displays G09G3/2003; grey scales specific for television H04N3/127
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: H10K 59/35 comprising red-green-blue [RGB] subpixels

Abstract

The disclosure relates to a data line demultiplexer, a display substrate, a display panel, and a display device. The data line demultiplexer includes a switching module, a plurality of switching signal terminals and a plurality of data signal terminals. The switching module is respectively connected to the plurality of switching signal terminals, the plurality of data signal terminals and M columns of pixel units in a display device. The switching module is capable of communicating each of the data signal terminals with at least two columns of sub-pixels under control of the plurality of switching signal terminals, wherein every two columns of sub-pixels that are connected with one data signal terminal are spaced apart by an odd number of columns of sub-pixels that are connected with other data signal terminals.

Claims

1. A data line demultiplexer, comprising a switching module, a plurality of switching signal terminals and a plurality of data signal terminals, wherein

the switching module is respectively connected to the plurality of switching signal terminals, the plurality of data signal terminals and M columns of pixel units in a display device, each column of pixel units comprising N columns of sub-pixels, where M is a positive integer, and N is an integer greater than 1;

any two adjacent columns of sub-pixels are controlled by different switching signal terminals, and the switching module selectively communicates each of the data signal terminals with at least two columns of sub-pixels under control of the plurality of switching signal terminals, wherein every two columns of sub-pixels that are connected with one data signal terminal are spaced apart by an odd number of columns of sub-pixels;

the switching module comprises k transistors, where k is the number of columns of sub-pixels in the display device; and

each of the k transistors has a gate electrode connected to one switching signal terminal, a first electrode connected to one data signal terminal, and a second electrode connected to one column of sub-pixels; and

the k transistors are divided into N groups and each group comprises M transistors; and

the gate electrodes of the M transistors in each group are connected to the same switching signal terminal, and the M columns of sub-pixels are connected to the second electrodes of the M transistors in each group are sub-pixels of the same color.

2. The data line demultiplexer according to claim 1, wherein every two columns of sub-pixels that are connected with one data signal terminal are spaced apart by one column of sub-pixels that are connected with other data signal terminals.

3. The data line demultiplexer according to claim 1, wherein the data line demultiplexer comprises N switching signal terminals.

4. The data line demultiplexer according to claim 1, wherein

each column of pixel units comprises three columns of sub-pixels of different colors;

and

the data line demultiplexer comprises three switching signal terminals.

5. The data line demultiplexer according to claim 1, wherein

the k transistors are all N-type transistors.

6. The data line demultiplexer according to claim 1, wherein the data line demultiplexer comprises M data signal terminals.

7. The data line demultiplexer according to claim 6, wherein the switching module selectively and respectively communicates each of the data signal terminals with the N columns of sub-pixels under control of the plurality of switching signal terminals.

8. The data line demultiplexer according to claim 1, wherein the data line demultiplexer comprises N switching signal terminals;

and

the gate electrodes of transistors of any two groups are connected to different switching signal terminals, and the second electrodes of transistors of any two groups are connected to sub-pixels of different colors.

9. The data line demultiplexer according to claim 8, wherein

the data line demultiplexer comprises M data signal terminals;

each of the data signal terminals is respectively connected to the first electrodes of the N transistors of the k transistors, and two adjacent transistors of the N transistors are spaced apart by one transistor in the data line demultiplexer; and

the second electrode of the i^th transistor in the k transistors is connected to the i^th column of sub-pixels, where i is a positive integer less than or equal to k.

10. The data line demultiplexer according to claim 8, wherein

the data line demultiplexer comprises M data signal terminals;

each of the data signal terminals is respectively connected to the first electrodes of N adjacent transistors of the k transistors; and

among the N columns of sub-pixels connected to the second electrodes of the N adjacent transistors, every two columns of sub-pixels that are connected with one data signal terminal are spaced apart by one column of sub-pixels that are connected with other data signal terminals.

11. A display substrate, comprising the data line demultiplexer according to claim 1.

12. A display panel, comprising the display substrate according to claim 11.

13. A display device, comprising the display panel according to claim 12.

14. A driving method for a data line demultiplexer, the data line demultiplexer comprising a switching module, a plurality of switching signal terminals, and a plurality of data signal terminals, wherein the switching module is respectively connected to the plurality of switching signal terminals, the plurality of data signal terminals and M columns of pixel units in a display device, each column of pixel units comprises N columns of sub-pixels of different colors, where M is a positive integer, and N is an integer greater than 1;

any two adjacent columns of sub-pixels are controlled by different switching signal terminals, and the switching module selectively communicates each of the data signal terminals with at least two columns of sub-pixels under control of the plurality of switching signal terminals, every two columns of sub-pixels that are connected with one data signal terminal are spaced apart by an odd number of columns of sub-pixels;

the switching module comprises k transistors, where k is the number of columns of sub-pixels in the display device, and each of the k transistors has a gate electrode connected to one switching signal terminal, a first electrode connected to one data signal terminal, and a second electrode connected to one column of sub-pixels; and

the k transistors are divided into N groups and each group comprises M transistors, the gate electrodes of the M transistors in each group are connected to the same switching signal terminal, and the M columns of sub-pixels connected to the second electrodes of the M transistors in each group are sub-pixels of the same color, and the method comprising;

during a process of displaying one frame of image, sequentially outputting, by the plurality of switching signal terminals, voltage signals for turning on corresponding transistors in the switching module, a voltage polarity of the data signal output by each of the plurality of data signal terminals remaining unchanged, and voltage polarities of data signals output by adjacent data signal terminals being opposite to each other; and

when a next frame of image is displayed, changing the voltage polarity of the data signal output by each of the plurality of data signal terminals.

15. The driving method according to claim 14, wherein during a process of displaying the next frame of image, the plurality of switching signal terminals sequentially output voltage signals that turn on corresponding transistors in the switching module.

16. The driving method according to claim 14, wherein every two columns of sub-pixels that are connected with one data signal terminal are spaced apart by one column of sub-pixels that are connected with other data signal terminals.