Semiconductor device

• US 10,643,671 B2
• Filed: 02/15/2018
• Issued: 05/05/2020
• Est. Priority Date: 09/20/2017
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tatsumura, Kosuke, Ikeda, Keiji, Tezuka, Tsutomu
• Primary Examiner(s): King, Douglas
• Application Number:
  US15/897,596
• Publication Number:
  US 20190088288A1
• Time in Patent Office: 810 Days
• Field of Search: None
• CPC Class Codes: G06F 5/10 having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory G06F5/065 takes precedence
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: G11C 19/282 with charge storage in a depletion layer, i.e. charge coupled devices [CCD]
• CPC Class Codes: G11C 19/287 Organisation of a multiplicity of shift registers
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

According to an embodiment, a semiconductor device includes a plurality of first interconnections, a plurality of gate dielectric films, and a plurality of second interconnections. The plurality of first interconnections are oxide semiconductors formed in parallel at predetermined intervals in a first direction. The plurality of gate dielectric films are formed on surfaces of the first interconnections, respectively. The plurality of second interconnections are conductors formed at predetermined intervals in parallel to a second direction orthogonal to the first direction, respectively, to bridge over the gate dielectric films.

Claims

1. A semiconductor device comprising:

a plurality of first interconnections that are oxide semiconductors formed in parallel at predetermined intervals in a first direction on a first layer;

a plurality of gate dielectric films that are formed on surfaces of the first interconnections, respectively;

a plurality of second interconnections that are conductors formed at predetermined intervals in parallel to a second direction on the first layer on which the first interconnections are formed, the second interconnections bridging over the gate dielectric films, the second direction being parallel to the first layer and being orthogonal to the first direction;

a plurality of charge injectors that are provided to correspond to the first interconnections in a one-to-one relation;

a transfer controller configured to control voltages to be applied to the second interconnections to move charges injected to respective start ends of the first interconnections in a direction toward a terminal end being an opposite end to a start end; and

a plurality of detectors that are provided to correspond to the first interconnections in a one-to-one relation, wherein

each of the charge injectors is configured to inject charges to the start end of a corresponding one of the first interconnections according to input data, and

each of the detectors is configured to extract charges held in the terminal end of a corresponding one of the first interconnections and output data according to the extracted charges.

2. The device according to claim 1, wherein

each of the first interconnections is divided into a plurality of columns in the first direction,

each of the columns is a region corresponding to a predetermined number of second interconnections and holds therein charges corresponding to data of one sample, the predetermined number being larger than or equal to 2,

each of the charge injectors is configured to inject charges corresponding to input data of one sample to a top column placed on the start end of a corresponding one of the first interconnections, and

each of the detectors is configured to extract charges corresponding to output data of one sample from a last column placed on the terminal end of a corresponding one of the first interconnections.

3. The device according to claim 2, wherein the transfer controller is configured to move charges held in each column to a column adjacent in a direction toward the terminal end when charges are extracted from the last column.

4. The device according to claim 3, wherein

the transfer controller includes

a plurality of flag storages that are provided to correspond to the columns in a one-to-one relation, and

a controller,

each of the flag storages is configured to store therein a flag indicating whether charges held in a corresponding one of the columns are valid,

a flag indicating that charges are valid is written to one of the flag storages corresponding to the top column when charges according to valid input data are injected to the top column, and

when charges are extracted from the last column, the controller is configured to move charges held in respective columns to columns adjacent in a direction to the terminal end, and move flags stored in ones of the flag storages corresponding to the respective columns to ones of the flag storages corresponding to the columns adjacent in the direction to the terminal end.

5. The device according to claim 4, wherein when a flag indicating that charges are not valid is stored in any of the flag storages, the controller is configured to move charges held in columns closer to the start end than a column corresponding to the flag storage in which the flag indicating that charges are not valid is stored, to columns adjacent in the direction to the terminal end, and move flags stored in ones of the flag storages corresponding to the columns closer to the start end than the column corresponding to the flag storage in which the flag indicating that charges are not valid is stored, to ones of the flag storages corresponding to the columns adjacent in the direction to the terminal end.

6. The semiconductor device according to claim 1, further comprising a demultiplexer configured to time-divide a serial data string with a bit width W input in synchronization with a clock of a first frequency into n pieces of parallel input data, and distribute the n pieces of input data to (W×

n) charge injectors, respectively, where n is an integer larger than or equal to 2, wherein

the transfer controller is configured to move charges injected into the start end of each of the first interconnections in synchronization with a clock of a second frequency that is obtained by dividing the first frequency by n.

7. The device according to claim 1, further comprising a multiplexer configured to time-multiplex plural pieces of output data output from the detectors in synchronization with a clock of a third frequency to generate serial data synchronized with a clock of a fourth frequency that is obtained by multiplying the third frequency by m and outputs the generated serial data, where m is an integer larger than or equal to 2.

8. The device according to claim 1, further comprising a switching unit configured to select either data received from outside or output data output from a corresponding one of the detectors, and provide a corresponding one of the charge injectors with the selected data as input data in response to a control signal.

9. The device according to claim 1, further comprising a substrate, wherein

the first interconnections are formed on the substrate, and

the substrate includes a semiconductor circuit that functions as the charge injectors, the transfer controller, and the detectors.

10. The device according to claim 1, further comprising a spacer that is an insulator formed to fill spaces between adjacent ones of the second interconnections, wherein

each of the first interconnections is an oxide semiconductor containing indium, gallium, and zinc, and

each of the second interconnections is metal.

11. The device according to claim 1, wherein

each of the first interconnections is wire-shaped, and

each of the second interconnections is wire-shaped.

12. A semiconductor device comprising:

a plurality of first interconnections that are oxide semiconductors formed in parallel at predetermined intervals in a first direction on a first layer;

a plurality of gate dielectric films that are formed on surfaces of the first interconnections, respectively;

a plurality of second interconnections that are conductors formed at predetermined intervals in parallel to a second direction on the first layer on which the first interconnections are formed, the second interconnections bridging over the gate dielectric films, the second direction being parallel to the first layer and being orthogonal to the first direction; and

a spacer that is an insulator formed to fill spaces between adjacent ones of the second interconnections, wherein

each of the first interconnections contains indium, gallium, and zinc, and

each of the second interconnections is metal.