Control circuit, sampling circuit for synchronous dynamic random-access memory, method of reading procedure and calibration thereof
First Claim
1. A memory control circuit for processing a reading data procedure with a memory, wherein the memory transmits a DQ and a DQS indicating presenting time of the DQ in the reading data procedure, wherein the DQS comprises a preamble and a tristate portion followed by the preamble, wherein the memory control circuit comprises:
- a clock generating circuit configured to generate a clock;
a control circuit coupled to the clock generating circuit, configured to generate an enabling signal based on the clock, and configured to transmit a control signal to the memory so as to make a signal level of the tristate portion maintain at a fixed level different from a signal level of the preamble; and
a sampling circuit coupled to the control circuit, and configured to sample the DQS to obtain a sampling level based on the enabling signal;
wherein the control circuit determines whether the sampling level matches a signal level of the preamble or not.
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Accused Products
Abstract
The present disclosure provides a memory control circuit configured to precede a data-reading process with a memory. For the data-reading process, the memory transmits a DQ and a DQS indicating a time to read the DQ. The DQS includes a preamble. The memory control circuit includes a control circuit and a sampling circuit. The control circuit is configured to generate an enabling signal. The sampling circuit coupled to the control circuit is configured to sample the DQS based on the enabling signal in order to determine a sampling level. The control circuit determines whether the sampling level matches a signal level of the preamble or not.
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Citations
18 Claims
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1. A memory control circuit for processing a reading data procedure with a memory, wherein the memory transmits a DQ and a DQS indicating presenting time of the DQ in the reading data procedure, wherein the DQS comprises a preamble and a tristate portion followed by the preamble, wherein the memory control circuit comprises:
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a clock generating circuit configured to generate a clock; a control circuit coupled to the clock generating circuit, configured to generate an enabling signal based on the clock, and configured to transmit a control signal to the memory so as to make a signal level of the tristate portion maintain at a fixed level different from a signal level of the preamble; and a sampling circuit coupled to the control circuit, and configured to sample the DQS to obtain a sampling level based on the enabling signal; wherein the control circuit determines whether the sampling level matches a signal level of the preamble or not. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A calibrating method configured to a reading data procedure between a memory control circuit and a memory, the memory control circuit comprises a clock generating circuit, a control circuit and a sampling circuit, wherein the memory transmits a DQ and a DQS indicating presenting time of the DQ in the reading data procedure, wherein the DQS comprises a preamble and a tristate portion followed by the preamble, wherein the method comprises:
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generating a clock by the clock generating circuit; generating an enabling signal by the control circuit; transmitting a control signal to the memory by the control circuit so as to make a signal level of the tristate portion maintain at a fixed level different from a signal level of the preamble; sampling the DQS based on the enabling signal by the sampling circuit to obtain a sampling level; and determining whether the sampling level matches a signal level of the preamble or not by the control circuit. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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Specification