Static random access memory (SRAM) tracking cells and methods of forming the same
First Claim
1. A memory array comprising:
- a first plurality of writable memory cells; and
a first cell comprising;
a first pair of cross-coupled inverters;
a first transistor connected to a first node of the first pair of cross-coupled inverters, wherein a voltage applied to a gate of the first transistor is directly tied to a voltage of a first supply voltage line; and
a second transistor, wherein the first transistor serially connects the second transistor to a first ground line, wherein the second transistor comprises a source/drain connected to a read tracking bit line (BL), and wherein the read tracking BL is connected to a read sense amplifier (SA) timing control circuit of the memory array.
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Abstract
An embodiment static random access memory (SRAM) array includes a writable SRAM cell disposed in a first row of the SRAM array and an SRAM read current tracking cell in the first row of the SRAM array. The SRAM current tracking cell includes a first read pull-down transistor and a first read pass-gate transistor. The first read pull-down transistor includes a first gate electrically connected to a first positive supply voltage line; a first source/drain electrically connected to a first ground line; and a second source/drain. The first read pass-gate transistor includes a third source/drain electrically connected to the second source/drain and a fourth source/drain electrically connected to a read tracking bit line (BL). The read tracking BL is electrically connected to a read sense amplifier timing control circuit.
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Citations
20 Claims
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1. A memory array comprising:
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a first plurality of writable memory cells; and a first cell comprising; a first pair of cross-coupled inverters; a first transistor connected to a first node of the first pair of cross-coupled inverters, wherein a voltage applied to a gate of the first transistor is directly tied to a voltage of a first supply voltage line; and a second transistor, wherein the first transistor serially connects the second transistor to a first ground line, wherein the second transistor comprises a source/drain connected to a read tracking bit line (BL), and wherein the read tracking BL is connected to a read sense amplifier (SA) timing control circuit of the memory array. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A memory array comprising:
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a first plurality of writable memory cells; and a first cell in a same row of the memory array as the first plurality of writable memory cells, the first cell comprising; a first pair of cross-coupled inverters; a first transistor connected to an output of the first pair of cross-coupled inverters; a second transistor, wherein the first transistor serially connects the second transistor to ground, wherein the second transistor comprises; a gate, wherein a voltage applied to the gate of the second transistor is directly tied to a voltage of a first ground line; and a source/drain connected to a read tracking bit line (BL), wherein the read tracking BL is connected to a read sense amplifier (SA) timing control circuit of the memory array. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A memory array comprising:
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a first invertor comprising a first transistor and a second transistor sharing a first gate electrode; a third transistor sharing the first gate electrode with the first transistor and the second transistor, the third transistor comprising a first source/drain region electrically connected to a first ground line; and a fourth transistor sharing a second source/drain region with the third transistor, wherein the fourth transistor comprises a second gate electrode and a third source/drain region, and wherein the second source/drain region is between the first gate electrode and the second gate electrode; a first gate contact electrically connecting the second gate electrode to a second ground line; and a first source/drain contact electrically connecting the third source/drain region to a first tracking bit line (BL), wherein the tracking BL is electrically connected to a sense amplifier (SA) timing control circuit. - View Dependent Claims (17, 18, 19, 20)
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Specification