Semiconductor memory device

• US 10,643,704 B2
• Filed: 09/17/2018
• Issued: 05/05/2020
• Est. Priority Date: 05/28/2018
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Oh, Sung-Lae, Kim, Dong-Hyuk, Jung, Soo-Nam
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US16/132,762
• Publication Number:
  US 20190362792A1
• Time in Patent Office: 596 Days
• Field of Search: 36513006
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

A semiconductor memory device includes a memory structural body including first and second planes each of which includes memory cells coupled to word lines extending in a first direction and bit lines extending in a second direction and which are disposed along the first direction; and a logic structural body disposed between a substrate and the memory structural body, and including a row decoder. The row decoder includes a pass transistor circuit which is coupled in common to the first and second planes and a block switch circuit which controls the pass transistor circuit. The block switch circuit is disposed in first and second plane regions of the logic structural body which overlap with the first and second planes in a third direction perpendicular to the first and second directions, and the pass transistor circuit is disposed in an interval region between the first and second plane regions.

Claims

1. A semiconductor memory device comprising:

a memory structural body including first and second planes each of which includes memory cells coupled to a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction and which are disposed along the first direction; and

a logic structural body disposed between a substrate and the memory structural body, and including a row decoder,

wherein the row decoder includes a pass transistor circuit which is coupled in common to the first and second planes and a block switch circuit which controls the pass transistor circuit,

wherein the block switch circuit is disposed in first and second plane regions of the logic structural body which overlap with the first and second planes in a third direction perpendicular to the first and second directions, and

wherein the pass transistor circuit is disposed in an interval region between the first plane region and the second plane region,

wherein the pass transistor circuit includes a plurality of pass transistors, each of the pass transistors is coupled in common to the word line of the first plane and the word line of the second plane, and provides an operating voltage simultaneously to the word line of the first plane and the word line of the second plane.

2. The semiconductor memory device according to claim 1, wherein the block switch circuit is disposed adjacent to the interval region.

3. The semiconductor memory device according to claim 1,

wherein each of the first and second planes comprises:

a plurality of gate electrode layers and a plurality of dielectric layers alternately stacked over a base layer; and

channel structures coupled to the base layer by passing through the gate electrode layers and the dielectric layers in the third direction, and

wherein the first and second planes have step structures which expose the gate electrode layers, at edges adjacent to the interval region.

4. A semiconductor memory device comprising:

a memory structural body including first and second planes each of which includes memory cells coupled to a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction and which are disposed along the first direction; and

a logic structural body disposed between a substrate and the memory structural body, and including a row decoder,

wherein the row decoder includes a pass transistor circuit which is coupled in common to the first and second planes and a block switch circuit which controls the pass transistor circuit,

wherein the block switch circuit is disposed in first and second plane regions of the logic structural body which overlap with the first and second planes in a third direction perpendicular to the first and second directions, and

wherein the pass transistor circuit is disposed in an interval region between the first plane region and the second plane region,

wherein the logic structural body further includes;

a first page buffer circuit disposed in the first plane region, and electrically coupled to the bit lines of the first plane; and

a second page buffer circuit disposed in the second plane region, and electrically coupled to the bit lines of the second pane,

wherein the first plane region includes a first region and a second region which are divided by a first virtual line extending in the first direction, and the second plane region includes a third region and a fourth region which are divided by the first virtual line,

wherein the first and second page buffer circuits are disposed in the first and third regions, respectively, and

wherein the block switch circuit includes first and second sub block switch circuits which are disposed in the second and fourth regions, respectively.

5. The semiconductor memory device according to claim 4, wherein the first and fourth regions are adjacent to each other in the first direction, and the second and third regions are adjacent to each other in the first direction.

6. The semiconductor memory device according to claim 4, wherein the first sub block switch circuit is disposed to have the same length as the second region in the second direction, and the second sub block switch circuit is disposed to have the same length as the fourth region in the second direction.

7. The semiconductor memory device according to claim 4, wherein the first and second page buffer circuits are disposed to have shapes which extend along the first direction.

8. The semiconductor memory device according to claim 7, further comprising:

first bit line contacts disposed in first bit line contact regions which are adjacent to both edges of the first page buffer circuit in the second direction, and electrically coupling the bit lines coupled to the first plane and the first page buffer circuit; and

second bit line contacts disposed in second bit line contact regions which are adjacent to both edges of the second page buffer circuit in the second direction, and electrically coupling the bit lines coupled to the second plane and the second page buffer circuit.

9. The semiconductor memory device according to claim 8, wherein first bit line contact region which is disposed close to the first virtual line, among the first bit line contact regions, and second bit line contact region which is disposed close to the first virtual line, among the second bit line contact regions, are offset in the second direction.

10. The semiconductor memory device according to claim 4,

wherein the first plane region includes a first region and a second region which are disposed at opposite sides of a dummy region extending in the first direction, and the second plane region includes a third region and a fourth region which are disposed at opposite sides of the dummy region,

wherein the first and second page buffer circuits are disposed in the first and third regions, respectively, and

wherein the block switch circuit includes first and second sub block switch circuits which are disposed in the second and fourth regions, respectively.

11. The semiconductor memory device according to claim 10, wherein the first and fourth regions are adjacent in the first direction, and the second and third regions are adjacent in the first direction.

12. The semiconductor memory device according to claim 11, further comprising:

first bit line contacts disposed in first bit line contact regions which are adjacent to both edges of the first page buffer circuit in the second direction, and electrically coupling the bit lines coupled to the first plane and the first page buffer circuit; and

second bit line contacts disposed in second bit line contact regions which are adjacent to both edges of the second page buffer circuit in the second direction, and electrically coupling the bit lines coupled to the second plane and the second page buffer circuit.

13. The semiconductor memory device according to claim 12, wherein one among the first bit line contact regions and one among the second bit line contact regions are disposed in the dummy region.

14. The semiconductor memory device according to claim 13, wherein one among the first bit line contact regions and one among the second bit line contact regions are disposed in a line along the first direction.

15. A semiconductor memory device comprising:

a memory structural body including first and second planes each of which includes a plurality of memory cells and which are disposed along a first direction; and

a logic structural body disposed between a substrate and the memory structural body, and including a row decoder which simultaneously controls the first and second planes and first and second page buffer circuits which control the first and second planes, respectively,

wherein the row decoder includes a pass transistor circuit and a block switch circuit which controls the pass transistor circuit,

wherein the first and second page buffer circuits overlap with the first and second planes, respectively, and are disposed to have shapes which extend in the first direction,

wherein the block switch circuit includes first and second sub block switch circuits which overlap with the first and second planes, respectively, and are disposed to have shapes which extend in a second direction, and

wherein the pass transistor circuit is disposed in a region between the first plane and the second plane, and includes a plurality of pass transistors which are coupled in common to the first and second planes,

wherein the pass transistor circuit includes a plurality of pass transistors, each of the pass transistors is coupled in common to the word line of the first plane and the word line of the second plane, and provides an operating voltage simultaneously to the word line of the first plane and the word line of the second plane.

16. The semiconductor memory device according to claim 15, wherein the first and second planes perform specific operations in parallel or independently.

17. The semiconductor memory device according to claim 15, wherein the pass transistor circuit extends along the second direction intersecting with the first direction, and is disposed to have the same length as the first and second planes in the second direction.

18. The semiconductor memory device according to claim 15, wherein the block switch circuit is disposed adjacent to the pass transistor circuit in the first direction.

19. A semiconductor memory device comprising:

a memory structural body including first and second planes disposed along a first direction, each having memory cells coupled to word lines extending in the first direction and bit lines extending in a second direction; and

a logic structural body including a row decoder,

wherein the row decoder has;

a pass transistor circuit coupled to the first and second planes, and disposed in an interval region between first and second plane regions overlapping with the first and second planes in a third direction; and

a block switch circuit configured to control the pass transistor circuit, and disposed in the first and second plane regions,

wherein the pass transistor circuit includes a plurality of pass transistors, each of the pass transistors is coupled in common to the word line of the first plane and the word line of the second plane, and provides an operating voltage simultaneously to the word line of the first plane and the word line of the second plane.