Group write operations for a data storage device

• US 10,643,707 B2
• Filed: 07/25/2017
• Issued: 05/05/2020
• Est. Priority Date: 07/25/2017
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Rajamani, Thibash, Chander, Ramesh, Krishnan, Manavalan, O'Krafka, Brian, Chodem, Nagi Reddy
• Primary Examiner(s): Rigol, Yaima
• Application Number:
  US15/659,208
• Publication Number:
  US 20190035473A1
• Time in Patent Office: 1,015 Days
• Field of Search: 711103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0623 for memory modules
• CPC Class Codes: G06F 12/0817 using directory methods
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/105 Circuits or methods for updating contents of nonvolatile memory, especially with 'security' features to ensure reliable replacement, i.e. preventing that old data is lost before new data is reliably written

Abstract

An apparatus includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller is configured to receive a command from a device to perform a write operation at the non-volatile memory. The command indicates a plurality of logical addresses, data associated with the plurality of logical addresses, and a number of write operations associated with the command.

Claims

1. An apparatus comprising:

a non-volatile memory; and

a controller coupled to the non-volatile memory, the controller configured to;

receive a command from a host device to perform a write operation at the non-volatile memory, the command including;

a plurality of non-sequential logical addresses of a plurality of write operations aggregated in the command;

data associated with the plurality of non-sequential logical addresses of the plurality of write operations aggregated in the command;

a number to indicate how many aggregated random write operations are associated with the command and aggregated by the host device, wherein the number is two or more; and

store the data associated with the plurality of non-sequential logical addresses in a physically contiguous area of the non-volatile memory.

2. The apparatus of claim 1, wherein:

the command further includes a write serialization (WS) group write opcode to indicate the data is to be written as a group; and

the controller is further configured to;

detect the WS group write opcode; and

in response, select the physically contiguous area of the non-volatile memory for storage of the data.

3. The apparatus of claim 2, further comprising a flash translation layer (FTL) of the controller, the FTL configured to determine a particular physical address of the non-volatile memory based on the plurality of logical addresses and the WS group write opcode.

4. The apparatus of claim 1, wherein the controller is further configured to:

perform the write operation to store the data to the non-volatile memory; and

update multiple entries of a logical-to-physical (L2P) address mapping table in response to the write operation.

5. The apparatus of claim 1 wherein the controller is configured to identify the command as a group write command from one or more addresses included in the plurality of non-sequential logical addresses.

6. The apparatus of claim 5 wherein the one or more addresses are invalid addresses or addresses reserved for group write commands.

7. The apparatus of claim 1 wherein the non-volatile memory is a monolithic three dimensional non-volatile memory including one or more memory device levels formed above a substrate.

8. The apparatus of claim 1 further comprising a host interface configured to communicate with the host device according to a communication protocol, wherein the communication protocol is one of Universal Serial Bus (USB) protocol, embedded MultiMedia Card (eMMC) protocol, Universal Flash Storage (UFS) protocol, or Secure Digital (SD) protocol.

9. The apparatus of claim 1 wherein the command corresponds to an extension of an interface protocol.

10. The apparatus of claim 1 wherein the command is a modification of a Frame Information Structure (FIS) of a Small Computer System Interface (SCSI) protocol, a Serial Attached SCSI (SAS) protocol, or a Serial Advanced Technology Attachment (SATA) protocol.

11. A method comprising:

receiving, by a data storage device that includes a non-volatile memory, a command from a host device to perform a write operation at the non-volatile memory, the command including;

a plurality of non-sequential logical addresses of a plurality of aggregated random write operations aggregated in the command;

data associated with the plurality of non-sequential logical addresses of the plurality of aggregated random write operations;

a write serialization (WS) group write opcode to indicate the data is to be written as a group; and

an indicator of the number of aggregated random write operations associated with the command, wherein the number is two or more, the random write operations are aggregated by the host device, and the random write operations are directed to the non-volatile memory;

detecting a WS group write from the WS group write opcode; and

in response to detecting the WS group write, executing the command by storing the data in a physically contiguous area of the non-volatile memory.

12. The method of claim 11, wherein the aggregated write operations are aggregated in the host device until the data satisfies a threshold.

13. The method of claim 12, further comprising determining, using a flash translation layer (FTL) of the data storage device, a particular physical address of the non-volatile memory based on the plurality of logical addresses and the WS group write opcode.

14. The method of claim 11, further comprising updating multiple entries of a logical-to-physical (L2P) address mapping table in response to the write operation.

15. An apparatus comprising:

a non-volatile memory; and

means for receiving a command from a host device to perform a write operation at the non-volatile memory, the command including;

a plurality of non-sequential logical addresses of a plurality of write operations aggregated in the command;

data associated with the plurality of non-sequential logical addresses of the plurality of write operations aggregated in the command;

a number to indicate how many aggregated random write operations are associated with the command and aggregated by the host device, wherein the number is two or more; and

a write serialization (WS) group write opcode to indicate the data is to be written as a group; and

wherein the means for receiving the command is configured to;

detect the WS group write opcode; and

in response to detection of the WS group write opcode;

store the data associated with the plurality of non-sequential logical addresses in a physically contiguous area of the non-volatile memory; and

update a logical-to-physical address mapping table with physical locations of the plurality of non-sequential logical addresses.

16. The apparatus of claim 15 wherein the means for receiving the command is further configured to send one or more messages to the host device to indicate a status of execution of the command.

17. The apparatus of claim 16 wherein the means for receiving the command is configured to send a message to indicate overall status of execution of the command.

18. The apparatus of claim 16 wherein the means for receiving the command is configured to send a message for each of the aggregated random write operations.

19. The apparatus of claim 15 wherein the non-volatile memory is a monolithic three dimensional non-volatile memory including one or more memory device levels formed above a substrate.

20. The apparatus of claim 15 wherein the non-volatile memory is a Resistive Random Access Memory (ReRAM).