Toggling power supply for faster bit line settling during sensing

• US 10,643,713 B1
• Filed: 02/08/2019
• Issued: 05/05/2020
• Est. Priority Date: 02/08/2019
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Louie, Kenneth, Amarnath, Anirudh
• Primary Examiner(s): Chen, Xiaochun L
• Application Number:
  US16/271,615
• Time in Patent Office: 452 Days
• Field of Search: 36518521
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/08 Control thereof

Abstract

A memory device and associated techniques improve a settling time of bit lines in a memory device during a sensing operation, such as read or verify operation. Supply voltage from power supply terminals in the sense circuits is briefly toggled during a discharge of a selected bit line in response to a voltage on a selected word line being increased to a second word line level or higher. This helps to create an electrical path from the selected bit line through to a supply terminal for discharging the selected bit line such that a settling time of a voltage of the selected bit line is shortened in association with a target memory cell transitioning from a non-conductive state to a conductive state.

Claims

1. An apparatus, comprising:

a control circuit coupled to a set of memory cells, the control circuit comprising;

a row decoder circuit configured to increase a sensing voltage on a selected word line coupled to the set of memory cells; and

a voltage supply circuit configured to lower a supply voltage to a sense circuit responsive to the sense circuit sensing a first data state of a memory cell such that a voltage of a selected bit line discharges through a voltage terminal that supplies the supply voltage in association with the memory cell transitioning from a non-conductive state to a conductive state, the memory cell coupled to the selected bit line.

2. The apparatus of claim 1, wherein:

the voltage supply circuit is configured to lower the supply voltage relative to the increase of the sensing voltage.

3. The apparatus of claim 1, wherein:

the voltage supply circuit is configured to lower the supply voltage from a first level to ground.

4. The apparatus of claim 3, wherein:

the voltage supply circuit is further configured to raise the supply voltage from the ground back up to the first level in response to the voltage of the selected bit line discharging from an initial level to a new level.

5. The apparatus of claim 4, further comprising:

the sense circuit configured to sense a second data state of the memory cell in response to the voltage supply circuit raising the supply voltage.

6. The apparatus of claim 3, wherein the voltage supply circuit is configured to lower the supply voltage from the first level to ground to shorten a settling time of the voltage of the selected bit line by a factor of about 10.

7. The apparatus of claim 1, wherein:

the row decoder circuit is configured to apply a series of increasing sensing voltages to the selected word line during a sequential sensing operation; and

the voltage supply circuit is configured to lower the supply voltage relative to the increase of the sensing voltage to a second level or higher in the series of the increasing sensing voltages.

8. The apparatus of claim 1, wherein the voltage of the selected bit line is discharged through a path connecting the selected bit line to the voltage terminal.

9. A system comprising:

a control circuit coupled to a set of memory cells and configured to sense a data state of a memory cell coupled to a bit line, the control circuit comprising;

a row decoder circuit configured to increase a sensing voltage from a first read level to a second read level on a word line coupled to the set of memory cells;

a current sense circuit configured to sense the data state of the memory cell corresponding to the sensing voltage; and

in response to the current sense circuit sensing a first data state of the memory cell, a voltage supply circuit configured to decrease, from a first level to a second level, a supply voltage to the current sense circuit to accelerate discharge of a capacitance of the bit line through a voltage terminal supplying the supply voltage while the memory cell conducts a cell current in relation to the sensing voltage at the second read level.

10. The system of claim 9, wherein the voltage supply circuit is further configured to hold the supply voltage at the second level for a predetermined duration of time and then increase the supply voltage from the second level to the first level.

11. The system of claim 9, wherein the voltage supply circuit is further configured to increase the supply voltage from the second level back up to the first level in response to a settling of a voltage of the bit line.

12. The system of claim 9, wherein the current sense circuit is further configured to sense a second data state of the memory cell in response to a settling of a voltage of the bit line.

13. The system of claim 9, wherein the first level is a range between about 2.2V and about 2.5V and the second level is a range between about 0V and about 1V.

14. The system of claim 9, wherein a rate of settling of a voltage of the bit line is proportional to a difference in voltage drop between the first level and the second level.

15. The system of claim 9, wherein the discharge of the capacitance of the bit line through the voltage terminal reduces a settling time of a voltage of the bit line by a factor about 10.

16. A method comprising:

raising, during sensing of data states, a voltage on a selected word line from a first sensing voltage to a second sensing voltage, the selected word line coupled to a set of memory cells;

in response to sensing a first data state of a memory cell, sinking current from a selected bit line of the memory cell through a voltage terminal driving the selected bit line by ramping down a supply voltage of the voltage terminal during a turning on of the memory cell in relation to the second sensing voltage; and

after a predetermined duration, ramping up the supply voltage of the voltage terminal.

17. The method of claim 16, wherein sinking the current settles a voltage of the selected bit line.

18. The method of claim 16, further comprising sensing a second data state of the memory cell in response to ramping up the supply voltage of the voltage terminal.

19. The method of claim 16, wherein sinking the current reduces a settling time of a voltage of the selected bit line from about 11 microseconds to about 1 microsecond.

20. The method of claim 16, wherein the predetermined duration is about 100 nanoseconds.