Toggling power supply for faster bit line settling during sensing
First Claim
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1. An apparatus, comprising:
- a control circuit coupled to a set of memory cells, the control circuit comprising;
a row decoder circuit configured to increase a sensing voltage on a selected word line coupled to the set of memory cells; and
a voltage supply circuit configured to lower a supply voltage to a sense circuit responsive to the sense circuit sensing a first data state of a memory cell such that a voltage of a selected bit line discharges through a voltage terminal that supplies the supply voltage in association with the memory cell transitioning from a non-conductive state to a conductive state, the memory cell coupled to the selected bit line.
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Abstract
A memory device and associated techniques improve a settling time of bit lines in a memory device during a sensing operation, such as read or verify operation. Supply voltage from power supply terminals in the sense circuits is briefly toggled during a discharge of a selected bit line in response to a voltage on a selected word line being increased to a second word line level or higher. This helps to create an electrical path from the selected bit line through to a supply terminal for discharging the selected bit line such that a settling time of a voltage of the selected bit line is shortened in association with a target memory cell transitioning from a non-conductive state to a conductive state.
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20 Claims
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1. An apparatus, comprising:
a control circuit coupled to a set of memory cells, the control circuit comprising; a row decoder circuit configured to increase a sensing voltage on a selected word line coupled to the set of memory cells; and a voltage supply circuit configured to lower a supply voltage to a sense circuit responsive to the sense circuit sensing a first data state of a memory cell such that a voltage of a selected bit line discharges through a voltage terminal that supplies the supply voltage in association with the memory cell transitioning from a non-conductive state to a conductive state, the memory cell coupled to the selected bit line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A system comprising:
a control circuit coupled to a set of memory cells and configured to sense a data state of a memory cell coupled to a bit line, the control circuit comprising; a row decoder circuit configured to increase a sensing voltage from a first read level to a second read level on a word line coupled to the set of memory cells; a current sense circuit configured to sense the data state of the memory cell corresponding to the sensing voltage; and in response to the current sense circuit sensing a first data state of the memory cell, a voltage supply circuit configured to decrease, from a first level to a second level, a supply voltage to the current sense circuit to accelerate discharge of a capacitance of the bit line through a voltage terminal supplying the supply voltage while the memory cell conducts a cell current in relation to the sensing voltage at the second read level. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A method comprising:
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raising, during sensing of data states, a voltage on a selected word line from a first sensing voltage to a second sensing voltage, the selected word line coupled to a set of memory cells; in response to sensing a first data state of a memory cell, sinking current from a selected bit line of the memory cell through a voltage terminal driving the selected bit line by ramping down a supply voltage of the voltage terminal during a turning on of the memory cell in relation to the second sensing voltage; and after a predetermined duration, ramping up the supply voltage of the voltage terminal. - View Dependent Claims (17, 18, 19, 20)
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Specification