Shielded vertically stacked data line architecture for memory
First Claim
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1. A memory array, comprising:
- multiple strings of vertically arranged memory cells, each memory cell including a charge storage structure, each memory cell string extending between a source and a respective bit line of multiple bit lines, wherein the bit lines extend in a first direction;
a first group of memory cell strings each selectively coupled to a first bit line through a respective select device in each memory cell string;
a second group of memory cell strings each selectively coupled to a second bit line through a respective select device in each memory cell string, wherein the second bit line is stacked above the first bit line, and wherein the first and second groups of memory cell strings are interleaved with one another along the first direction in which the first and second bit lines extend;
access lines coupled to respective memory cells in each of the first and second groups of memory cell strings, each access line configured to allow access to a respective memory cell in each of the first and second groups of memory cell strings to perform a memory operation involving such memory cell;
a memory controller configured to perform a shielded bit line sensing operation, in which the first bit line is coupled to a shield potential during at least a portion of sensing interval in which the state of a selected memory cell in a selected memory cell string of the second group of memory cell strings is sensed, and wherein during the sensing interval the selected memory cell is coupled to the second bit line.
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Abstract
Apparatuses and methods include an apparatus that includes first and second strings of vertically stacked memory cells, and first and second pluralities of vertically stacked data lines. A data line of the first plurality of data lines is coupled to the first string through a first select device. A data line of the second plurality of data lines is coupled to the second string through a second select device and is adjacent to the data line coupled to the first string. Such an apparatus can be configured to couple the data line coupled to the first string to a shield potential during at least a portion of a memory operation involving a memory cell of the second string.
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Citations
21 Claims
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1. A memory array, comprising:
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multiple strings of vertically arranged memory cells, each memory cell including a charge storage structure, each memory cell string extending between a source and a respective bit line of multiple bit lines, wherein the bit lines extend in a first direction; a first group of memory cell strings each selectively coupled to a first bit line through a respective select device in each memory cell string; a second group of memory cell strings each selectively coupled to a second bit line through a respective select device in each memory cell string, wherein the second bit line is stacked above the first bit line, and wherein the first and second groups of memory cell strings are interleaved with one another along the first direction in which the first and second bit lines extend; access lines coupled to respective memory cells in each of the first and second groups of memory cell strings, each access line configured to allow access to a respective memory cell in each of the first and second groups of memory cell strings to perform a memory operation involving such memory cell; a memory controller configured to perform a shielded bit line sensing operation, in which the first bit line is coupled to a shield potential during at least a portion of sensing interval in which the state of a selected memory cell in a selected memory cell string of the second group of memory cell strings is sensed, and wherein during the sensing interval the selected memory cell is coupled to the second bit line. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of operating a memory array having multiple vertical strings of memory cells, comprising:
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accessing selected memory cells from the multiple strings of memory cells, wherein the multiple strings of memory cells are arranged in rows and columns, each string having multiple vertically arranged memory cells and extending between a source and a respective bit line of multiple bit lines, wherein the bit lines extend in a first direction, and wherein first and second bit lines are vertically stacked relative to one another, wherein strings of memory cells that are adjacent to one another along the first direction are coupled to different bit lines, wherein the vertically arranged memory cells of the multiple strings are associated with respective access lines, and wherein the access lines are coupled to respective memory cells in each of a plurality of strings of the multiple strings; applying a pass voltage to access lines not associated with the selected memory cells; applying an operational voltage to a selected access line associated with the selected memory cells to enable the selected memory cells; coupling a first bit line of the multiple stacked bit lines to a shield voltage line during at least a portion of a memory operation; and wherein strings of memory cells comprising the enabled memory cells are operably coupled to the second bit line during the memory operation, and wherein strings of memory cells that do not contain the enabled memory cells are operably coupled to the first bit line during at least a portion of the memory operation. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A method, comprising:
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operating a memory array having multiple strings of memory cells, wherein each memory cell string extends vertically and includes multiple vertically arranged memory cells and extends between a source and a respective bit line of multiple bit lines, wherein the multiple bit lines extend in a first direction, and include a first group of bit lines and a second group of bit lines, wherein the bit lines of the second group are vertically stacked relative to respective bit lines of the first group, wherein strings of memory cells that are adjacent one another along the first direction are coupled to different bit lines, wherein the vertically arranged memory cells of the memory cell strings are associated with a respective access line, wherein the access lines are coupled to respective memory cells in each of multiple strings, and wherein the multiple memory cell strings are selectively coupled to a respective bit line through a respective select gate drain transistor; the operating of the memory array comprising, applying a read voltage to a selected access line of multiple access lines, each access line coupled to a respective memory cell in each string of a first group of strings of memory cells; applying a read pass voltage to unselected access lines of the multiple access lines; applying a pre-charge voltage to a first group of bit lines during a read operation; applying a shield voltage to a second group of bit lines during at least a portion of the read operation; and applying an enable voltage to select gate drain transistors of a second group of memory cell strings comprising the enabled memory cells to couple the second group of memory cell strings to respective bit lines of the second group of bit lines during the read operation. - View Dependent Claims (19, 20, 21)
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Specification