Semiconductor memory device and memory system configured to perform tracking read on first memory cells followed by shift read on second memory cells using read voltage correction value determined during the tracking read
First Claim
1. A semiconductor memory device comprising:
- a memory cell array including first memory cells and second memory cells;
a first word line connected to gates of the first memory cells;
a second word line connected to gates of the second memory cells; and
a control circuit configured to execute a first read operation in response to a first command set and a second read operation in response to a second command set, whereinthe first command set includes a first command which instructs the control circuit to apply at least first to third voltages to the first word line to determine a number of first, second, and third on-cells of the first memory cells, respectively, and to calculate a read voltage, which is used in a reading operation, based on the determined number of first, second, and third on-cells of the first memory cells, andthe second command set includes a second command which instructs the control circuit to read data from the second memory cells by applying the read voltage to the second word line.
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Accused Products
Abstract
A semiconductor memory device includes first, second, and third memory cells, and first, second, and third word lines that are respectively connected to gates of the first, second, and third memory cells. A control circuit executes first, second, and third read operations in response to first, second, and third command sets, respectively. The first read operation includes a first read sequence, in which the control circuit reads data by applying first to third voltages to the first word line. In the second read operation, the control circuit reads data by applying a second read voltage that is set based on a result of the first read sequence, to the second word line. In the third read operation, the control circuit reads data from the third memory cells by applying a second read voltage that is set independently of the result of the first read sequence, to the third word line.
15 Citations
16 Claims
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1. A semiconductor memory device comprising:
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a memory cell array including first memory cells and second memory cells; a first word line connected to gates of the first memory cells; a second word line connected to gates of the second memory cells; and a control circuit configured to execute a first read operation in response to a first command set and a second read operation in response to a second command set, wherein the first command set includes a first command which instructs the control circuit to apply at least first to third voltages to the first word line to determine a number of first, second, and third on-cells of the first memory cells, respectively, and to calculate a read voltage, which is used in a reading operation, based on the determined number of first, second, and third on-cells of the first memory cells, and the second command set includes a second command which instructs the control circuit to read data from the second memory cells by applying the read voltage to the second word line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of performing a read operation in a semiconductor memory device comprising a memory cell array including first memory cells and second memory cells, a first word line connected to gates of the first memory cells, and a second word line connected to gates of the second memory cells, said method comprising:
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in response to a first command set, applying at least first to third voltages to the first word line to read data from the first memory cells and calculating a read voltage, which is used in a reading operation, based on the data read; and in response to a second command set, applying the read voltage to the second word line to read data from the second memory cells. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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Specification