Semiconductor memory device and memory system configured to perform tracking read on first memory cells followed by shift read on second memory cells using read voltage correction value determined during the tracking read

  • US 10,643,715 B2
  • Filed: 11/19/2018
  • Issued: 05/05/2020
  • Est. Priority Date: 08/19/2016
  • Status: Active Grant
  • ×

    Create Patent Alert


    *Certain alert events are not available for your current subscription level. Upgrade
  • Save
  • 0Associated
    Cases
  • 0Associated
    Defendants
  • 0Accused
    Products
  • 0Forward
    Citations
  • 0
    Petitions
  • 0
    Assignments
    ×



    ×

    Thank you for your feedback

    ×
    ×