Non-volatile memory with countermeasure for program disturb including purge during precharge

• US 10,643,718 B2
• Filed: 06/07/2018
• Issued: 05/05/2020
• Est. Priority Date: 06/07/2018
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Zhao, Dengtao, Zhang, Peng, Lu, Nan, Dutta, Deepanshu
• Primary Examiner(s): Bashar, Mohammed A
• Application Number:
  US16/002,825
• Publication Number:
  US 20190378580A1
• Time in Patent Office: 698 Days
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.

Claims

1. An apparatus, comprising:

a plurality of non-volatile memory cells including a plurality of channels;

a plurality of control lines connected to the memory cells;

a programming circuit connected to the control lines, the programming circuit configured to apply a programming voltage to a selected control line to program selected memory cells connected to the selected control line;

a boosting circuit connected to the control lines, the boosting circuit configured to boost voltage of channels connected to unselected memory cells; and

a pre-charge circuit connected to the control lines, the pre-charge circuit configured to pre-charge the channels connected to unselected memory cells prior to boosting the voltage of the channels connected to unselected memory cells, the pre-charge circuit further configured to apply a bypass voltage to a programmed side unselected control line that is adjacent to the selected control line while pre-charging the channels connected to unselected memory cells, the pre-charge circuit configured to pre-charge the channels connected to unselected memory cells by applying a pre-charge voltage to unprogrammed side unselected control lines, the bypass voltage is greater than the pre-charge voltage, the bypass voltage comprises a voltage of a magnitude sufficient to cause memory cells receiving the bypass voltage to turn on regardless of which data state the memory cells are programmed or erased to.

2. The apparatus of claim 1, wherein:

the pre-charge circuit configured to pre-charge unprogrammed sides of the channels connected to unselected memory cells prior to boosting the voltage of the channels connected to unselected memory cells, the pre-charge circuit configured to apply the bypass voltage to the programmed side unselected control line that is adjacent to the selected control line while pre-charging unprogrammed sides of the channels connected to unselected memory cells.

3. The apparatus of claim 1, wherein:

the pre-charge circuit configured to pre-charge drain sides of the channels connected to unselected memory cells prior to boosting the voltage of the channels connected to unselected memory cells by applying pre-charge voltages to drain side unselected control lines, the pre-charge circuit configured to apply the bypass voltage to source side unselected control lines while pre-charging the drain side of channels connected to unselected memory cells, the source side and the drain side are with respect to the selected control line.

4. The apparatus of claim 1, wherein:

the pre-charge circuit configured to not pre-charge source sides of the channels connected to unselected memory cells while pre-charging drain sides of the channels connected to unselected memory cells; and

the pre-charge circuit configured to apply one or more voltages to source side unselected control that are too low to pre-charge and too low to turn on memory cells in a highest data state.

5. The apparatus of claim 1, wherein:

the plurality of control lines comprises a first stack of alternating control line layers and dielectric layers, a second stack of alternating control line layers and dielectric layers, and a joint area between the first stack and the second stack;

the selected control line is in the second stack; and

the applying the bypass voltage to the programmed unselected control line that is adjacent to the selected control line while pre-charging channels of the unselected groups maintains a programmed side of the channels of unselected groups to be in electrical communication with an unprogrammed side of the channels of unselected groups to allow electrons positioned in the joint area to move from the programmed side of the channels of unselected groups into the unprogrammed side of the channels of unselected groups.

6. An apparatus, comprising:

a plurality of non-volatile memory cells;

a plurality of control lines connected to the memory cells; and

a control circuit connected to the control lines, the control circuit configured to program a first subset of the memory cells connected to a selected control line and inhibit programming of a second subset of the memory cells connected to the selected control line by applying a programming signal to the selected control line and applying boosting signals to unselected control lines to boost channels for the second subset of the memory cells, the control circuit further configured to pre-charge channels for the second subset of the memory cells prior to the applying the boosting signals by applying a pre-charge voltage to not yet programmed unselected control lines and apply a bypass voltage to an already programmed unselected control line adjacent to the selected control line while pre-charging channels for the second subset of the memory cells, the bypass voltage comprises a voltage of a magnitude sufficient to cause memory cells receiving the bypass voltage to turn on regardless of which data state the memory cells are programmed or erased to.

7. The apparatus of claim 6, wherein:

the control circuit is configured apply one or more bypass voltages to multiple already programmed unselected control lines while pre-charging channels for the second subset of the memory cells.

8. The apparatus of claim 6, wherein:

the already programmed unselected control line adjacent to the selected control line is on a programmed side of the selected control line;

the not yet programmed unselected control lines are on a unprogrammed side of the selected control line;

the bypass voltage is greater than the pre-charge voltage; and

the pre-charge voltage is greater than zero volts.

9. The apparatus of claim 6, wherein:

the control circuit is configured to pre-charge channels for the second subset of the memory cells by applying positive voltage to unprogrammed side unselected control lines and programmed side unselected control lines, the already programmed side unselected control line adjacent to the selected control line is on a programmed side of the selected control line.

10. The apparatus of claim 6, wherein:

the control circuit is configured to pre-charge channels for the second subset of the memory cells by applying positive voltage to drain side unselected control lines, the already programmed side unselected control line adjacent to the selected control line is on a source side of the selected control line, the control circuit is configured to apply the bypass voltage to the already programmed side unselected control line adjacent to the selected control line while pre-charging drain side channels for the second subset of the memory cells.

11. The apparatus of claim 6, wherein:

the control circuit is configured to pre-charge unprogammed side channels for the second subset of the memory cells prior to the applying boosting signals by applying the pre-charge voltage to the not yet programmed unselected control lines and a third voltage to programmed side unselected control lines that are not adjacent to the selected control line, the bypass voltage is greater than the pre-charge voltage, the pre-charge voltage is greater than the third voltage, the third voltage is too low to pre-charge and too low to turn on memory cells in a highest data state.

12. The apparatus of claim 6, wherein:

the control circuit is configured to pre-charge drain side channels for the second subset of the memory cells prior to the applying boosting signals and apply the bypass voltage to the already programmed side unselected control line adjacent to the selected control line while pre-charging the drain side channels for the second subset of the memory cells, the already programmed side unselected control line adjacent to the selected control line is on a source side of the selected control line.

13. The apparatus of claim 6, wherein:

the control circuit is configured to pre-charge drain side and source side of channels for the second subset of the memory cells prior to the applying boosting signals and applying the bypass voltage to the already programmed side unselected control line adjacent to the selected control line while pre-charging the drain side and source side channels for the second subset of the memory cells, the already programmed side unselected control line adjacent to the selected control line is on the source side.

14. The apparatus of claim 6, wherein:

the plurality of control lines comprises a first stack of alternating word line layers and dielectric layers, a second stack of alternating word line layers and dielectric layers, and a joint area between the first stack and the second stack;

the selected control line is a selected word line in the second stack; and

the applying the bypass voltage puts a programmed side of the channels for the second subset of the memory cells to be in electrical communication with an unprogrammed side for the second subset of the memory cells to allow electrons positioned in the joint area to move from the programmed side of the channels for the second subset of the memory cells into the unprogrammed side of the channels for the second subset of the memory cells.

15. The apparatus of claim 6, wherein:

the control circuit configured to program the first subset of memory cells and inhibit programming of the second subset of memory cells by applying a programming allow signal to bit lines for the first subset of memory cells and applying an inhibit signal to bit lines for the second subset of memory cells;

the control lines are word lines;

the memory cells are arranged in vertical NAND strings with charge trapping regions; and

the memory cells, the plurality of control lines and the control circuit are on a same die.

16. A method, comprising:

applying a program voltage to a selected word line connected to a plurality of NAND strings;

boosting channels of unselected NAND strings;

pre-charging channels of at least a subset of the unselected NAND strings prior to the boosting by applying a pre-charge voltage to unprogrammed side unselected word lines; and

applying a bypass voltage to an already programmed side unselected word line adjacent to the selected word line while pre-charging, the bypass voltage is greater than the pre-charge voltage, the bypass voltage comprises a voltage of a magnitude sufficient to cause memory cells receiving the bypass voltage to turn on regardless of which data state the memory cells are programmed or erased to.

17. The method of claim 16, wherein:

the boosting channels include applying boosting voltages to unselected word lines prior to applying the program voltage to the selected word line; and

the pre-charging channels of at least a subset of the unselected NAND strings comprises pre-charging an unprogrammed side of the channels of at least the subset of the unselected NAND strings by applying pre-charge voltages to unprogrammed side unselected word lines prior to the applying boosting voltages to unselected word lines; and

the applying the bypass voltage comprises applying the bypass voltage to multiple programmed side unselected word lines while applying pre-charge voltages to unprogrammed side unselected word lines.

18. The method of claim 16, wherein:

the NAND strings include memory cells; and

the pre-charging channels further comprises applying a third voltage to already programmed side unselected word lines that are not adjacent to the selected control line, the pre-charge voltage is greater than the third voltage, the third voltage is too low to pre-charge and too low to turn on memory cells in a highest data state.

19. The method of claim 16, wherein:

the pre-charging channels of at least a subset of the unselected NAND strings comprises pre-charging a drain side and a source side of channels of unselected NAND strings.

20. The method of claim 16, wherein:

the selected word line and unselected word lines comprise a first stack of alternating word line layers and dielectric layers, a second stack of alternating word line layers and dielectric layers, and a joint area between the first stack and the second stack; and

the applying the bypass voltage to the already programmed side unselected word line adjacent to the selected word line while pre-charging causes electrons from the joint area to migrate from source side channel regions to drain side channel regions of unselected NAND strings.

21. An apparatus, comprising:

a monolithic three dimensional memory array comprising a lower set of alternating conductive and dielectric layers and an upper set of alternating conductive and dielectric layers separated by a joint area that together form a plurality of word lines and a plurality of vertical charge-trapping NAND strings each having a channel;

means for providing a series of programming pulses to a selected word line to program memory cells connected to the selected word line that are in selected NAND strings;

means for boosting the channels of unselected NAND strings;

means for pre-charging the channels of unselected NAND strings prior to boosting; and

means for applying a bypass voltage to an already programmed side unselected word line adjacent to the selected word line while pre-charging to cause a first side of the unselected NAND strings with respect to the selected word line to be in electrical communication with a second side of the unselected NAND strings, the bypass voltage comprises a voltage of a magnitude sufficient to cause memory cells receiving the bypass voltage to turn on regardless of which data state the memory cells are programmed or erased to.