Apparatus and methods for protection against inadvertent programming of fuse cells

• US 10,643,727 B2
• Filed: 06/12/2019
• Issued: 05/05/2020
• Est. Priority Date: 11/02/2016
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: Zhou, Bo, Blin, Guillaume Alexandre
• Primary Examiner(s): King, Douglas
• Application Number:
  US16/438,913
• Publication Number:
  US 20190295672A1
• Time in Patent Office: 328 Days
• Field of Search: None
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H10B 20/25 One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

Abstract

Apparatus and methods for protection against inadvertent programming of fuse cells are provided herein. In certain configurations, a fuse system includes a fuse protection diode, a fuse, a fuse programming transistor and a cascode transistor electrically connected in series between a cathode of the fuse protection diode and the fuse, a power supply pad electrically connected to an anode of the fuse protection diode and that receives a power supply voltage, and a biasing circuit powered by the power supply voltage and including a voltage regulator that generates a regulated voltage and a level shifter that provides a fuse programming signal to a gate of the fuse programming transistor. The level shifter controls the fuse programming signal with the power supply voltage in a first state of a control signal, and controls the fuse programming signal with the regulated voltage in a second state of the control signal.

Claims

1. A fuse system for a semiconductor die, the fuse system comprising:

a fuse protection diode;

a first fuse;

a first fuse programming transistor and a first cascode transistor electrically connected in series between a cathode of the fuse protection diode and the first fuse;

a power supply pad electrically connected to an anode of the fuse protection diode, the power supply pad configured to receive a power supply voltage; and

a biasing circuit powered by the power supply voltage and including a voltage regulator configured to generate a regulated voltage and a level shifter configured to provide a fuse programming signal to a gate of the first fuse programming transistor, the level shifter configured to control the fuse programming signal with the power supply voltage in a first state of a control signal, and to control the fuse programming signal with the regulated voltage in a second state of the control signal.

2. The fuse system of claim 1 further comprising a serial interface configured to provide the control signal to the biasing circuit to instruct programming of the first fuse.

3. The fuse system of claim 1 further comprising a ground pad configured to receive a ground voltage, the first fuse electrically connected between a drain of the first cascode transistor and the ground pad.

4. The fuse system of claim 1 further comprising a plurality of core circuits powered by the power supply voltage from the power supply pad.

5. The fuse system of claim 1 further comprising a second fuse, a second cascode transistor, and a second fuse programming transistor, the second cascode transistor and the second fuse programming transistor electrically connected in series between the second fuse and the cathode of the fuse protection diode.

6. The fuse system of claim 5 further comprising a shared fuse sensing circuit having a first input electrically connected to the first fuse and a second input electrically connected to the second fuse.

7. The fuse system of claim 1 wherein the voltage regulator is further configured to provide a cascode bias voltage to a gate of the first cascode transistor.

8. The fuse system of claim 7 further comprising a ground pad electrically connected to the first fuse, the voltage regulator further configured to generate the cascode bias voltage based on a voltage difference between the power supply pad and the ground pad.

9. The fuse system of claim 1 wherein the voltage regulator is a low dropout regulator.

10. The fuse system of claim 9 wherein the biasing circuit further includes a bandgap reference circuit powered by the power supply voltage and configured to provide a bandgap reference voltage to the low dropout regulator.

11. A method of protecting against accidental fuse programming, the method comprising:

providing a power supply voltage to a power supply pad, the power supply pad connected to an anode of a fuse protection diode;

powering a biasing circuit that biases a fuse programming transistor using the power supply voltage, the fuse programming transistor electrically connected in series with a cascode transistor between a cathode of the fuse protection diode and a fuse;

generating a regulated voltage using a voltage regulator of the biasing circuit; and

providing a gate of the fuse programming transistor with a fuse programming signal from a level shifter of the biasing circuit, including controlling the fuse programming signal with the power supply voltage in a first state of a control signal, and controlling the fuse programming signal with the regulated voltage in a second state of the control signal.

12. The method of claim 11 further comprising providing the control signal to the biasing circuit over a serial interface.

13. The method of claim 11 further comprising providing a cascode bias voltage to a gate of the cascode transistor using the voltage regulator.

14. The method of claim 13 further comprising generating the cascode bias voltage based on a voltage difference between the power supply pad and a ground pad.

15. A packaged module comprising:

a package substrate; and

a semiconductor die attached to the package substrate, the semiconductor die including a fuse protection diode, a first fuse, a first cascode transistor, a first fuse programming transistor electrically connected in series with the first cascode transistor between a cathode of the fuse protection diode and the first fuse, a power supply pad electrically connected to an anode of the fuse protection diode and configured to receive a power supply voltage, and a biasing circuit powered by the power supply voltage and including a voltage regulator configured to generate a regulated voltage and a level shifter configured to provide a fuse programming signal to a gate of the first fuse programming transistor, the level shifter configured to control the fuse programming signal with the power supply voltage in a first state of a control signal, and to control the fuse programming signal with the regulated voltage in a second state of the control signal.

16. The packaged module of claim 15 wherein the semiconductor die further includes a second fuse, a second cascode transistor, and a second fuse programming transistor, the second cascode transistor and the second fuse programming transistor electrically connected in series between the second fuse and the cathode of the fuse protection diode.

17. The packaged module of claim 16 wherein the semiconductor die further includes a shared fuse sensing circuit having a first input electrically connected to the first fuse and a second input electrically connected to the second fuse.

18. The packaged module of claim 15 wherein the semiconductor die further includes a plurality of core circuits powered by the power supply voltage from the power supply pad.

19. The packaged module of claim 15 wherein the voltage regulator is further configured to provide a cascode bias voltage to a gate of the first cascode transistor.

20. The packaged module of claim 19 wherein the semiconductor die further includes a ground pad electrically connected to the first fuse, the voltage regulator further configured to generate the cascode bias voltage based on a voltage difference between the power supply pad and the ground pad.