Passive array test structure for cross-point memory characterization
First Claim
1. A method for parallel testing of a plurality of memory cells disposed in a plurality of memory arrays built using a semiconductor substrate, the method comprising:
- creating a wafer containing the plurality of memory arrays, the wafer including at least one test memory array including a plurality of test memory cells, with each of the test memory cells having a word line and a bit line associated therewith, wherein the test memory array does not include a selector device associated therewith, and wherein the step of creating includes, after determining a selected plurality of test memory cells to test that is a subset of the plurality of test memory cells;
modifying a layout of connections within the test memory array between the selected plurality of test memory cells so that an unselected plurality of test memory cells is electrically disconnected from the selected plurality of test memory cells and the word lines and bit lines of the selected plurality of test memory cells are each connected to an associated test pad; and
modifying conductor layer patterns disposed above and below the selected plurality of test memory cells to minimize resistances between the selected plurality of test memory cells;
connecting a multi-channel parallel parametric tester to a selected plurality of test pads associated with the selected plurality of test memory cells;
using the multi-channel parallel parametric tester, grounding word lines associated with memory cells that are not within the selected subset plurality of test memory cells to test;
using the multi-channel parallel parametric tester, applying a predetermined test signal to each of the word lines associated with the selected plurality of test memory cells; and
using the multi-channel parallel parametric tester, measuring resistance values at each of the bit lines associated with the selected plurality of test memory cells.
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Accused Products
Abstract
An apparatus and method for testing two-terminal memory elements organized as a cross-point memory array. The apparatus allows functional testing of two-terminal memory elements organized as a cross-point memory array, and built in a short flow manufacturing process. The proposed apparatus substantially eliminates the use of any type of additional active or passive switches, selectors, or decoders. A large number of memory elements of various memory types including planar (two dimensional) or three dimensional memory structures can be tested without the need of manufacturing selectors or running the full flow process.
8 Citations
13 Claims
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1. A method for parallel testing of a plurality of memory cells disposed in a plurality of memory arrays built using a semiconductor substrate, the method comprising:
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creating a wafer containing the plurality of memory arrays, the wafer including at least one test memory array including a plurality of test memory cells, with each of the test memory cells having a word line and a bit line associated therewith, wherein the test memory array does not include a selector device associated therewith, and wherein the step of creating includes, after determining a selected plurality of test memory cells to test that is a subset of the plurality of test memory cells; modifying a layout of connections within the test memory array between the selected plurality of test memory cells so that an unselected plurality of test memory cells is electrically disconnected from the selected plurality of test memory cells and the word lines and bit lines of the selected plurality of test memory cells are each connected to an associated test pad; and modifying conductor layer patterns disposed above and below the selected plurality of test memory cells to minimize resistances between the selected plurality of test memory cells; connecting a multi-channel parallel parametric tester to a selected plurality of test pads associated with the selected plurality of test memory cells; using the multi-channel parallel parametric tester, grounding word lines associated with memory cells that are not within the selected subset plurality of test memory cells to test; using the multi-channel parallel parametric tester, applying a predetermined test signal to each of the word lines associated with the selected plurality of test memory cells; and using the multi-channel parallel parametric tester, measuring resistance values at each of the bit lines associated with the selected plurality of test memory cells. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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Specification