Semiconductor device and method for manufacturing the same

• US 10,643,844 B2
• Filed: 07/18/2019
• Issued: 05/05/2020
• Est. Priority Date: 03/30/2017
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Lee, Nam Jae
• Primary Examiner(s): Seven, Evren
• Application Number:
  US16/515,954
• Publication Number:
  US 20190341251A1
• Time in Patent Office: 292 Days
• Field of Search: None
• CPC Class Codes: H01L 21/02019 Chemical etching
• CPC Class Codes: H01L 21/02697 Forming conducting materials on a substrate
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

Provided herein is a method for manufacturing a semiconductor device. The method may include: forming a stack including at least one first material layer and at least one second material layer which are alternately stacked; forming first holes through which the at least one first material layer is exposed; forming etch stop patterns in the respective first holes; forming at least one slit passing through the stack; replacing the at least one first material layer with at least one third material layer through the at least one slit; and forming first contact plugs in the respective first holes, the first contact plugs passing through the etch stop patterns and coupled with the at least one third material layer.

Claims

1. A semiconductor device comprising:

a stack including at least one conductive layer and at least one insulating layer which are alternately stacked;

contact plugs passing through the stack to different depths;

etch stop patterns enclosing respective sidewalls of the contact plugs; and

protective patterns enclosing the respective etch stop patterns,

wherein the contact plugs pass through the etch stop patterns and the protective patterns, and are electrically coupled with the at least one conductive layer.

2. The semiconductor device according to claim 1, further comprising:

sacrificial patterns interposed between the contact plugs and the etch stop patterns.

3. The semiconductor device according to claim 2, wherein upper surfaces of the etch stop patterns and upper surfaces of the protective patterns are disposed lower than upper surfaces of the contact plugs.

4. The semiconductor device according to claim 1, further comprising:

channel layers passing through the stack.

5. The semiconductor device according to claim 4, wherein upper surfaces of the channel layers are lower than upper surfaces of the etch stop patterns.

6. The semiconductor device according to claim 4, wherein upper surfaces of the channel layers are lower than upper surfaces of the protective patterns.

7. The semiconductor device according to claim 1, further comprising:

dummy channel layers passing through the stack.

8. The semiconductor device according to claim 7, wherein the contact plugs are located between the dummy channel layers.

9. A semiconductor device comprising:

a stack including conductive layers and insulating layers which are alternately stacked;

a first contact plug passing through the stack to a first depth;

a first etch stop pattern enclosing a sidewall of the first contact plug;

a first protective pattern enclosing the first etch stop pattern;

a second contact plug passing through the stack to a second depth deeper than the first depth;

a second etch stop pattern enclosing a sidewall of the second contact plug; and

a second protective pattern enclosing the second etch stop pattern,

wherein the first contact plug passes through the first etch stop pattern and the first protective pattern, and is electrically coupled with a first conductive layer among the conductive layers.

10. The semiconductor device according to claim 9, wherein the second contact plug passes through the second etch stop pattern and the second protective pattern, and is electrically coupled with a second conductive layer among the conductive layers.

11. The semiconductor device according to claim 10, wherein the second conductive layer is located lower than the first conductive layer.

12. The semiconductor device according to claim 9, further comprising:

a first sacrificial pattern interposed between the first contact plug and the first etch stop pattern.

13. The semiconductor device according to claim 9, wherein an upper surface of the first etch stop pattern and an upper surface of the second etch stop pattern are located at substantially the same level.

14. The semiconductor device according to claim 13, wherein a lower surface of the second etch stop pattern is located lower than a lower surface of the first etch stop pattern.

15. The semiconductor device according to claim 9, further comprising:

a channel layer passing through the stack.

16. The semiconductor device according to claim 15, wherein an upper surface of the channel layer is lower than an upper surface of the first etch stop pattern.

17. The semiconductor device according to claim 15, wherein an upper surface of the channel layer is lower than an upper surface of the first protective pattern.

18. The semiconductor device according to claim 9, further comprising:

dummy channel layers passing through the stack.

19. The semiconductor device according to claim 18, wherein the first contact plug is located between the dummy channel layers.