Hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication

• US 10,643,859 B2
• Filed: 09/13/2018
• Issued: 05/05/2020
• Est. Priority Date: 09/09/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation, ZEON Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bruce, Robert L., Joseph, Eric A., Lee, Joe, Suzuki, Takefumi
• Primary Examiner(s): Lee, Hsien Ming
• Application Number:
  US16/130,596
• Publication Number:
  US 20190013209A1
• Time in Patent Office: 600 Days
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5329 Insulating materials

Abstract

In one embodiment, a method for hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication includes providing a layer of a dielectric material and etching a trench in the layer of the dielectric material, by applying a mixture of an aggressive dielectric etch gas and a polymerizing etch gas to the layer of the dielectric material. In another embodiment, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices. A pitch of the plurality of conductive lines is approximately twenty-eight nanometers.

Claims

1. An integrated circuit, comprising:

a front end, comprising;

a semiconductor wafer; and

a first plurality of semiconductor devices formed on the semiconductor wafer; and

a back end, comprising;

a dielectric layer;

a plurality of interconnects formed in the dielectric layer for electrically connecting a second plurality of semiconductor devices in the back end; and

a carbon-containing layer positioned directly between the dielectric layer and each interconnect of the plurality of interconnects.

2. The integrated circuit of claim 1, wherein the plurality of interconnects comprises copper.

3. The integrated circuit of claim 1, wherein the plurality of interconnects comprises a copper alloy.

4. The integrated circuit of claim 1, wherein the plurality of interconnects comprises gold.

5. The integrated circuit of claim 1, wherein the plurality of interconnects comprises nickel.

6. The integrated circuit of claim 1, wherein the plurality of interconnects comprises cobalt.

7. The integrated circuit of claim 1, wherein the plurality of interconnects comprises silver.

8. The integrated circuit of claim 1, wherein the plurality of interconnects comprises ruthenium.

9. The integrated circuit of claim 1, wherein a pattern density of the plurality of interconnects has a pitch of approximately twenty-eight nanometers.

10. The integrated circuit of claim 1, wherein the plurality of interconnects has a uniform profile.

11. The integrated circuit of claim 3, further comprising:

a capping layer positioned directly between the dielectric layer and the front end.

12. The integrated circuit of claim 11, wherein the capping layer comprises silicon nitride.

13. The integrated circuit of claim 11, wherein the capping layer comprises silicon carbonitride.

14. The integrated circuit of claim 11, wherein the capping layer comprises silicon oxycarbonitride.

15. The integrated circuit of claim 1, wherein the dielectric layer comprises a low-k dielectric.

16. The integrated circuit of claim 1, wherein the dielectric layer comprises an ultra-low-k dielectric.

17. The integrated circuit of claim 1, wherein the dielectric layer comprises silicon dioxide.