Metal loss prevention using implantation

• US 10,643,892 B2
• Filed: 05/31/2018
• Issued: 05/05/2020
• Est. Priority Date: 05/31/2018
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wu, Li-Chieh, Chang, Tang-Kuei, Wei, Kuo-Hsiu, Chen, Kei-Wei, Wang, Ying-Lang, Liu, Su-Hao, Chen, Kuo-Ju, Chen, Liang-Yin, Chang, Huicheng, Chang, Ting-Kui, Lee, Chia Hsuan
• Primary Examiner(s): Reddington, Patricia D
• Application Number:
  US15/993,768
• Publication Number:
  US 20190371664A1
• Time in Patent Office: 705 Days
• CPC Class Codes: H01L 2029/7858 having contacts specially adapted to the FinFET geometry, e.g. wrap-around contacts
• CPC Class Codes: H01L 21/31155 by ion implantation
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76825 by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc. plasma treatment H01L21/76826
• CPC Class Codes: H01L 21/7684 Smoothing; Planarisation
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 21/76886 Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.

Claims

1. A method for semiconductor processing, the method comprising:

depositing a conductive feature in a dielectric layer, wherein the conductive feature is in direct contact with the dielectric layer;

after depositing the conductive feature, implanting an implant species into the dielectric layer;

after implanting the implant species, removing a portion of the conductive feature by a first planarization process;

after removing the portion of the conductive feature, implanting another implant species into the dielectric layer; and

after implanting the another implant species, removing another portion of the conductive feature and the dielectric layer by a second planarization process.

2. The method of claim 1, wherein the implant species comprises at least one of Geranium (Ge), Silicon (Si), and Nitrogen (N).

3. The method of claim 1, wherein implanting the implant species comprises expanding the dielectric layer to form an expanded dielectric layer, the expanded dielectric layer applying a compressive force to the conductive feature.

4. The method of claim 1, wherein a peak concentration point of the implant species in the dielectric layer is in a portion of the dielectric layer removed by the first second planarization process.

5. The method of claim 1 further comprising forming an opening through the dielectric layer to expose a conductive material in a layer under the dielectric layer, wherein depositing the conductive feature comprises growing the conductive feature in the opening in a bottom-up manner.

6. The method of claim 1, wherein implanting the implant species into the dielectric layer is performed at an angle from an axis that is perpendicular to a surface of the dielectric layer, the angle being greater than zero.

18. The method of claim 1, wherein implanting another implant species is performed at a lower energy level than implanting the implant species.

7. A method for semiconductor processing, the method comprising:

depositing a dielectric material over a substrate having a conductive material;

forming an opening in the dielectric material to expose the conductive material;

depositing a conductive feature in the opening and directly contacting the conductive material, wherein depositing the conductive feature forms an overfill portion above the dielectric material;

performing a first implantation process to implant an implant species in the dielectric material;

after performing the first implantation process, performing a first planarization process to remove a portion of the conductive feature, wherein performing the first planarization process removes the overfill portion of the conductive material;

after performing the first planarization process, performing a second implantation process to implant another implant species in the dielectric material; and

after performing the second implantation process, performing a second planarization process to remove a portion of the dielectric material and a portion of the conductive material.

8. The method of claim 7, wherein depositing the conductive feature comprises growing the conductive feature in the opening in a bottom-up manner.

9. The method of claim 7, wherein the dielectric material comprises an etch stop layer and an interlayer dielectric above the etch stop layer.

10. The method of claim 7, wherein implanting the implant species comprises implanting a neutral element in the dielectric material to expand the dielectric material to apply compression around the conductive feature.

11. The method of claim 7, wherein performing the first implantation process comprises directing the implant species towards the dielectric material at a non-zero angle relative to an axis perpendicular to a surface of the dielectric material, the surface of the dielectric material being distal from the substrate.

19. The method of claim 7, wherein the implant species and the another implant species are one or more species of neutral elements.

20. The method of claim 7 further comprising performing an anneal after the second implantation process.

12. A method for semiconductor processing, the method comprising:

depositing a dielectric material over a substrate;

forming an opening in the dielectric material to expose a conductive feature;

filling the opening with a conductive material, wherein a gap is interposed between the conductive material and a sidewall of the opening;

performing a first implantation process to implant an implant species in the dielectric material, wherein a width of the gap decreases after performing the first implantation process;

after performing the first implantation process, performing a first planarization process to remove a portion of the conductive material;

after performing the first planarization process, performing a second implantation process to implant another implant species in the dielectric material; and

after performing the second implantation process, performing a second planarization process to remove a portion of the dielectric material and a portion of the conductive material, wherein the implant species and the another implant species are one or more neutral species.

13. The method of claim 12, wherein the implant species comprises Geranium (Ge), Silicon (Si), or Nitrogen (N).

14. The method of claim 12, wherein a peak concentration of the implant species is in a range from 8×

10¹⁸ atoms/cm³ to 1×

10²¹ atoms/cm³.

15. The method of claim 12, further comprising forming an etch stop layer over the substrate, wherein the dielectric material is deposited over the etch stop layer, wherein the conductive material is disposed through the etch stop layer.

16. The method of claim 15, wherein the etch stop layer comprises the implant species, a concentration of the implant species in the etch stop layer being in a range from about 2×

10¹⁸ atoms/cm³ to about 6×

10²⁰ atoms/cm³.

17. The method of claim 12, wherein the dielectric material comprises a silicon oxide, silicon oxynitride, silicon oxycarbide, or a combination thereof.