Methods for forming a semiconductor device and related semiconductor device structures

• US 10,643,904 B2
• Filed: 10/27/2017
• Issued: 05/05/2020
• Est. Priority Date: 11/01/2016
• Status: Active Grant

• Current Assignee: ASM IP Holding B.V. (ASM International NV)
• Original Assignee: ASM IP Holdings B.V.
• Inventors: Xie, Qi, Givens, Michael Eugen, Raisanen, Petri, Maes, Jan Willem
• Primary Examiner(s): Oh, Jaehwan
• Application Number:
  US15/796,593
• Publication Number:
  US 20180122709A1
• Time in Patent Office: 921 Days
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

Methods for forming a semiconductor device and related semiconductor device structures are provided. In some embodiments, methods may include forming an NMOS gate dielectric and a PMOS gate dielectric over a substrate and forming a first work function metal over the NMOS gate dielectric and over the PMOS gate dielectric. In some embodiments, methods may also include, removing the first work function metal over the NMOS gate dielectric and forming a second work function metal over the NMOS gate dielectric and over the PMOS gate dielectric. In some embodiments, related semiconductor device structures may include an NMOS gate dielectric and a PMOS gate dielectric disposed over a semiconductor substrate. A PMOS gate electrode may be disposed over the PMOS gate dielectric and the PMOS gate electrode may include a first work function metal disposed over the PMOS gate dielectric and a second work function metal disposed over the first work function metal. A NMOS gate electrode may be disposed over the NMOS gate dielectric and the NMOS gate electrode may include the second work function metal.

Claims

1. A method for forming a semiconductor device comprising:

forming an interface layer on a surface of a semiconductor substrate, wherein the interface layer is disposed in an NMOS trench region and a PMOS trench region;

forming an NMOS gate dielectric over the interface layer in the NMOS trench region and a PMOS gate dielectric over the interface layer in the PMOS trench region;

forming a first work function metal directly on the NMOS gate dielectric and directly on the PMOS gate dielectric;

removing the first work function metal over the NMOS gate dielectric; and

forming a second work function metal directly on the NMOS gate dielectric and directly on the first work function metal over the PMOS gate dielectric,

wherein the first work function metal comprises a metal nitride and wherein the second work function metal comprises at least one of a transition metal carbide and a transition metal aluminide.

2. The method of claim 1, wherein forming the interface layer comprises utilizing a selective chemical oxidation process.

3. The method of claim 2, wherein the method further comprises forming spacers extending along sides of the NMOS trench region and the PMOS trench region before forming the interface layer, such that the interface layer is formed and extends between the spacers.

4. The method of claim 1, wherein the first work function metal comprises a niobium titanium nitride.

5. The method of claim 1, wherein removing the first work function metal over the NMOS gate dielectric further comprises:

selectively etching the first work function metal.

6. The method of claim 1, wherein the second work function metal comprises niobium-aluminum carbide (NbAlC).

7. The method of claim 1, wherein the second work function metal comprises a transition metal carbide selected from the group consisting of tantalum carbide (TaC), titanium carbide (TiC), titanium-aluminum carbide (TiAlC), and niobium-aluminum carbide (NbAlC).

8. The method of claim 1, wherein the second work function metal comprises a transition metal aluminide selected from the group consisting of titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), and hafnium aluminide (HfAl).

9. A method for forming a CMOS semiconductor device comprising:

forming an NMOS gate dielectric and a PMOS gate dielectric over a semiconductor substrate;

depositing by atomic layer deposition a niobium nitride layer directly onto the NMOS gate dielectric and directly onto the PMOS gate dielectric;

etching the niobium nitride layer over the NMOS gate dielectric;

depositing by atomic layer deposition at least one of a transition metal aluminide and a transition metal carbide directly onto the NMOS gate dielectric and directly onto the niobium nitride layer that is over the PMOS gate dielectric;

depositing a liner material over the at least one of the transition metal aluminide and the transition metal carbide; and

depositing a metal fill material over the liner material.

10. The method of claim 9, wherein the niobium nitride layer comprises a niobium titanium nitride.

11. The method of claim 9, wherein the transition metal aluminide comprises at least one of:

titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), and hafnium aluminide (HfAl).

12. The method of claim 9, wherein the transition metal carbide comprises at least one of:

tantalum carbide (TaC), titanium carbide (TiC), titanium-aluminum carbide (TiAlC), and niobium-aluminum carbide (NbAlC).

13. The method of claim 9, wherein the liner material comprises titanium nitride and the metal fill material comprises tungsten.

14. A semiconductor device structure comprising:

an interface layer disposed over a semiconductor substrate in an NMOS trench region and a PMOS trench region;

an NMOS gate dielectric disposed over the interface layer in the NMOS trench region and a PMOS gate dielectric disposed over the interface layer in the PMOS trench region;

a PMOS gate electrode disposed over the PMOS gate dielectric, the PMOS gate electrode comprising;

a first work function metal disposed directly on the PMOS gate dielectric; and

a second work function metal disposed directly on the first work function metal; and

an NMOS gate electrode disposed over the NMOS gate dielectric, the NMOS gate electrode comprising the second work function metal directly on the NMOS gate dielectric,

wherein the first work function metal comprises a metal nitride and wherein the second work function metal comprises at least one of a transition metal carbide and a transition metal aluminide.

15. The semiconductor device structure of claim 14, wherein the first work function metal comprises a niobium nitride.

16. The semiconductor device structure of claim 15, wherein the niobium nitride comprises a niobium titanium nitride.

17. The semiconductor device structure of claim 14, wherein the second work function metal comprises niobium-aluminum carbide (NbAlC).

18. The semiconductor device structure of claim 14, wherein the transition metal carbide comprises at least one of:

tantalum carbide (TaC), titanium carbide (TiC), a titanium-aluminum carbide (TiAlC), and a niobium-aluminum carbide (NbAlC).

19. The semiconductor structure of claim 14, wherein the transition metal aluminide comprises at least one of:

titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), and hafnium aluminide (HfAl).

20. The semiconductor device structure of claim 14, wherein the interface layer is disposed between spacers in respective trench regions.