Methods of forming a transistor and methods of forming an array of memory cells

• US 10,643,906 B2
• Filed: 12/15/2017
• Issued: 05/05/2020
• Est. Priority Date: 12/15/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Hwang, David K., Smythe, John A., Liu, Haitao, Hill, Richard J., Pandey, Deepak Chandra
• Primary Examiner(s): Malek, Maliheh
• Application Number:
  US15/843,493
• Publication Number:
  US 20190189515A1
• Time in Patent Office: 872 Days
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 29/1041 with a non-uniform doping structure in the channel region surface
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H10B 12/482 Bit lines
• CPC Class Codes: H10B 12/485 Bit line contacts
• CPC Class Codes: H10B 12/488 Word lines
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

An embodiment of the invention comprises a method of forming a transistor comprising forming a gate construction having an elevationally-outermost surface of conductive gate material that is lower than an elevationally-outer surface of semiconductor material that is aside and above both sides of the gate construction. Tops of the semiconductor material and the conductive gate material are covered with masking material, two pairs of two opposing sidewall surfaces of the semiconductor material are laterally exposed above both of the sides of the gate construction. After the covering, the semiconductor material that is above both of the sides of the gate construction is subjected to monolayer doping through each of the laterally-exposed two opposing sidewall surfaces of each of the two pairs and forming there-from doped source/drain regions above both of the sides of the gate construction.

Claims

1. A method of forming a transistor, comprising:

forming a gate construction having an elevationally-outermost surface of conductive gate material that is lower than an elevationally-outer surface of semiconductor material that is aside and above both sides of the gate construction;

covering tops of the semiconductor material and the conductive gate material with masking material, two pairs of two opposing sidewall surfaces of the semiconductor material being laterally exposed above both of the sides of the gate construction; and

after the covering, monolayer doping the semiconductor material that is above both of the sides of the gate construction through each of the laterally-exposed two opposing sidewall surfaces of each of the two pairs and forming there-from doped source/drain regions above both of the sides of the gate construction.

2. The method of claim 1 wherein the covering of the tops of the semiconductor material with the masking material and the covering of the top of the conductive gate material with the masking material occur over different time-spaced periods of time.

3. The method of claim 2 wherein the covering of the tops of the semiconductor material with the masking material occurs before the covering of the top of the conductive gate material with the masking material.

4. The method of claim 1 wherein the covering forms the masking material atop the semiconductor material and the masking material atop the conductive gate material to comprise different compositions relative one another.

5. The method of claim 1 wherein the elevationally-outer surface of the semiconductor material that is above both of the sides of the gate construction is the elevationally-outermost surface of the semiconductor material that is above both of the sides of the gate construction.

6. The method of claim 1 wherein the covering of the tops of the conductive gate material comprises:

depositing the masking material laterally over two facing sidewall surfaces of the semiconductor material that is above both of the sides of the gate construction, the two facing sidewall surfaces individually being a different one of the two opposing sidewall surfaces from a different one of the two pairs; and

elevationally recessing the masking material that is laterally over said two facing sidewall surfaces and to leave the top of the conductive gate material covered by the masking material.

7. The method of claim 6 wherein the gate construction comprises gate insulator material aside the conductive gate material, the gate insulator material also extending elevationally along said two facing sidewall surfaces, the covering comprising:

forming the masking material laterally aside the gate insulator material that extends elevationally along said two facing sidewall surfaces; and

elevationally recessing the gate insulator material that extends elevationally along said two facing sidewall surfaces.

8. The method of claim 7 wherein,

the gate insulator material and the masking material that is laterally aside the gate insulator material that extends elevationally along said two facing sidewall surfaces are of the same composition relative one another;

and

the elevationally recessing of the masking material that is laterally over said two facing sidewall surfaces and the elevationally recessing of the gate insulator material that extends elevationally along said two facing sidewall surfaces comprising chemical etching said gate insulator material and said masking material at the same time.

9. The method of claim 8 wherein,

the covering forms the masking material atop the semiconductor material and the masking material atop the conductive gate material to comprise different compositions relative one another;

and

the chemical etching being conducted selectively relative to the masking material that is atop the semiconductor material.

10. The method of claim 7 wherein after the elevationally recessings, the masking material that is laterally aside the gate insulator material that extends elevationally along said two facing sidewall surfaces and the gate insulator material that extends elevationally along said two facing sidewall surfaces have respective elevationally-outermost surfaces that are at a common elevation above the conductive gate material.

11. The method of claim 1 wherein,

the monolayer doping comprises:

forming of a self-assembled covalently-bonded dopant-containing monolayer directly on each of the laterally-exposed two opposing sidewall surfaces of each of the two pairs;

forming a dielectric covering material directly on the dopant-containing monolayers; and

diffusing dopants from the dopant-containing monolayers having the dielectric covering material thereon into the semiconductor material that is above both of the sides of the gate construction through each of the two opposing sidewall surfaces of each of the two pairs and forming there-from the doped source/drain regions; and

not removing at least some of the dielectric covering material after the diffusing and which remains as part of a finished circuit construction that comprises the transistor.

12. The method of claim 11 comprising not removing any of the dielectric covering material after the diffusing.

13. The method of claim 1 wherein,

the monolayer doping comprises:

forming of a self-assembled covalently-bonded dopant-containing monolayer directly on each of the laterally-exposed two opposing sidewall surfaces of each of the two pairs;

forming a covering material directly on the dopant-containing monolayers; and

diffusing dopants from the dopant-containing monolayers having the covering material thereon into the semiconductor material that is above both of the sides of the gate construction through each of the two opposing sidewall surfaces of each of the two pairs and forming there-from the doped source/drain regions; and

removing all of the covering material after the diffusing.

14. A method of forming a transistor, comprising:

forming a gate construction having an elevationally-outermost surface of conductive gate material that is lower than an elevationally-outermost surface of semiconductor material that is aside and above both sides of the gate construction; and

monolayer doping the semiconductor material that is above both of the sides of the gate construction and forming there-from doped source/drain regions above both of the sides of the gate construction, the monolayer doping being conducted in a vertically-self-aligned manner through two pairs of opposing sidewall surfaces of the semiconductor material that is above both of the sides of the gate construction.

15. A method of forming a transistor, comprising:

forming a gate construction having an elevationally-outermost surface of conductive gate material that is lower than an elevationally-outer surface of semiconductor material that is aside and above both sides of the gate construction;

covering tops of the semiconductor material and the conductive gate material with masking material, two pairs of two opposing sidewall surfaces of the semiconductor material being laterally exposed above both of the sides of the gate construction;

forming a dopant monolayer directly on each of the laterally-exposed two opposing sidewall surfaces of each of the two pairs;

forming a covering material directly on the dopant monolayers; and

diffusing dopants from the dopant monolayers having the covering material thereon into the semiconductor material that is above both of the sides of the gate construction through each of the two opposing sidewall surfaces of each of the two pairs and forming there-from doped source/drain regions above both of the sides of the gate construction.

16. The method of claim 15 comprising forming the dopant monolayers by atomic layer deposition.

17. The method of claim 15 comprising monolayer doping wherein forming the dopant monolayers is by formation of a self-assembled covalently-bonded dopant-containing monolayer directly on each of the laterally-exposed two opposing sidewall surfaces of each of the two pairs.

18. A method of forming an array of memory cells, comprising:

forming recessed-access-gate-line constructions within semiconductor material, the recessed-access-gate-line constructions individually having an elevationally-outermost surface of conductive gate material that is lower than an elevationally-outermost surface of the semiconductor material that is aside and above both sides of the individual recessed-access-gate-line construction, laterally-spaced pairs of the recessed-access-gate-line constructions individually comprising a digit-line-contact region laterally-inward between the recessed-access-gate-line constructions of the pair of the recessed-access-gate-line constructions and a capacitor-contact region laterally-outward of each of the recessed-access-gate-line constructions of the pair of the recessed-access-gate-line constructions;

covering tops of the semiconductor material and the conductive gate material with masking material, two pairs of two opposing sidewall surfaces of the semiconductor material being laterally exposed above both of the sides of the individual recessed-access-gate-line constructions;

after the covering, monolayer doping the semiconductor material that is above both of the sides of the individual recessed-access-gate-line constructions through each of the laterally-exposed two opposing sidewall surfaces of each of the two pairs and forming there-from doped source/drain regions above both of the sides of the individual recessed-access-gate-line constructions, the source/drain region laterally-inward between the recessed-access-gate-line constructions of individual of the pairs of the recessed-access-gate-line constructions comprising individual of the digit-line-contact regions, the source/drain regions laterally-outward of each of the recessed-access-gate-line constructions of the individual pairs of the recessed-access-gate-line constructions comprising individual of the capacitor-contact regions; and

after the monolayer doping, forming capacitors individually electrically coupled to the individual capacitor-contact regions and forming digit lines individually electrically coupled to the individual digit-line-contact regions.

19. The method of claim 18 wherein,

individual first conductive vias are formed which individually directly electrically couple individual of the capacitors to the individual capacitor-contact regions;

individual second conductive vias are formed which individually directly electrically couple individual of the digit lines to the individual digit-line-contact regions; and

at least one of (a) the first conductive vias, and (b) the second conductive vias being directly against respective tops of their individual capacitor-contact region or individual digit-line-contact region.

20. The method of claim 18 wherein,

individual first conductive vias are formed which individually directly electrically couple individual of the capacitors to the individual capacitor-contact regions;

individual second conductive vias are formed which individually directly electrically couple individual of the digit lines to the individual digit-line-contact regions; and

at least one of (a) the first conductive vias, and (b) the second conductive vias being directly against a respective sidewall of their individual capacitor-contact region or individual digit-line-contact region.

21. A method of forming an array of memory cells, comprising:

forming recessed-access-gate-line constructions within semiconductor material, the recessed-access-gate-line constructions individually having an elevationally-outermost surface of conductive gate material that is lower than an elevationally-outermost surface of the semiconductor material that is aside and above both sides of the individual recessed-access-gate-line construction, laterally-spaced pairs of the recessed-access-gate-line constructions individually comprising a digit-line-contact region laterally-inward between the recessed-access-gate-line constructions of the pair of the recessed-access-gate-line constructions and a capacitor-contact region laterally-outward of each of the recessed-access-gate-line constructions of the pair of the recessed-access-gate-line constructions;

covering tops of the semiconductor material and the conductive gate material with masking material, two pairs of two opposing sidewall surfaces of the semiconductor material being laterally exposed above both of the sides of the individual recessed-access-gate-line constructions;

forming a dopant monolayer directly on each of the laterally-exposed two opposing sidewall surfaces of each of the two pairs above both of the sides of the individual recessed-access-gate-line constructions;

forming a covering material directly on the dopant monolayers;

diffusing dopants from the dopant monolayers having the covering material thereon into the semiconductor material that is above both of the sides of the individual recessed-access-gate-line constructions through each of the two opposing sidewall surfaces of each of the two pairs for the individual recessed-access-gate-line constructions and forming there-from doped source/drain regions above both of the sides of the individual recessed-access-gate-line constructions, the source/drain region laterally-inward between the recessed-access-gate-line constructions of individual of the pairs of the recessed-access-gate-line constructions comprising individual of the digit-line-contact regions, the source/drain regions laterally-outward of each of the recessed-access-gate-line constructions of the individual pairs of the recessed-access-gate-line constructions comprising individual of the capacitor-contact regions; and

after the diffusing, forming capacitors individually electrically coupled to the individual capacitor-contact regions and forming digit lines individually electrically coupled to the individual digit-line-contact regions.