Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step

• US 10,643,907 B2
• Filed: 01/03/2019
• Issued: 05/05/2020
• Est. Priority Date: 12/14/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kerber, Pranita, Ouyang, Qiqing C., Reznicek, Alexander, Schepis, Dominic J.
• Primary Examiner(s): Roman, Angel
• Application Number:
  US16/239,107
• Publication Number:
  US 20190157167A1
• Time in Patent Office: 488 Days
• Field of Search: None
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02502 consisting of two layers
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/7849 the means being provided under the channel

Abstract

A method of making a semiconductor device includes forming a first silicon germanium layer on a substrate, the first silicon germanium layer forming a portion of a first transistor; forming a second silicon germanium layer on the substrate adjacent to the first silicon germanium layer, the second silicon germanium layer forming a portion of a second transistor and having a germanium content that is different than the first silicon germanium layer and a thickness that is substantially the same; growing by an epitaxial process a compressively strained silicon germanium layer on the first silicon germanium layer, and a tensile strained silicon germanium layer on the second silicon germanium layer; patterning a first fin in the compressively strained silicon germanium layer and the first silicon germanium layer; and patterning a second fin in the tensile strained silicon germanium layer and the second silicon germanium layer.

Claims

1. A method of making a semiconductor device, the method comprising:

forming a first fin of a first transistor on a substrate, the first fin comprising a first relaxed silicon germanium layer; and

forming a second fin of a second transistor adjacent to the first fin of the first transistor, the second fin comprising a second relaxed silicon germanium layer arranged on the substrate and a tensile strained silicon germanium layer arranged on the second relaxed silicon germanium layer, the second relaxed silicon germanium layer comprising a germanium content that is different than the first relaxed silicon germanium layer.

2. The method of claim 1, wherein the first transistor is a pFET.

3. The method of claim 2, wherein the second transistor is an nFET.

4. The method of claim 1, wherein a germanium content of the tensile strained silicon germanium layer is less than a germanium content of the second relaxed silicon germanium layer.

5. The method of claim 4, further comprising a compressively strained layer arranged on the first relaxed silicon germanium layer.

6. The method of claim 4, wherein the germanium content of the tensile strained silicon germanium layer is greater than a germanium content of the first relaxed silicon germanium layer.

7. The method of claim 5, wherein the germanium content of the compressively strained silicon germanium layer is greater than a germanium content of the first relaxed silicon germanium layer.

8. The method of claim 5, wherein the compressively strained strained silicon germanium layer and the tensile strained silicon germanium layer have a germanium content that is substantially the same.

9. The method of claim 5, wherein a thickness of the compressively strained silicon germanium layer is in a range from about 10 to about 50 nm.

10. The method of claim 1, wherein a thickness of the first relaxed silicon germanium layer of the first transistor is in a range from about 6 to about 1000 nm.

11. The method of claim 1, wherein a thickness of the second relaxed silicon germanium layer of the second transistor is in a range from about 6 to about 1000 nm.

12. The method of claim 1, wherein a thickness of the the tensile strained silicon germanium layer is in a range from about 10 to about 50 nm.

13. A method of making a semiconductor device, the method comprising:

forming a first fin on a substrate, the first fin comprising a silicon germanium layer; and

forming a second fin on the substrate, the second fin comprising a relaxed silicon germanium layer and a tensile strained silicon germanium layer arranged on the relaxed silicon germanium layer, the relaxed silicon germanium layer comprising a germanium content that is different than the silicon germanium layer.

14. The method of claim 13, wherein the first fin is a portion of a pFET.

15. The method of claim 13, wherein the second second fin is a portion of an nFET.

16. The method of claim 13, wherein a germanium content of the tensile strained silicon germanium layer is less than a germanium content of the relaxed silicon germanium layer.

17. The method of claim 16, further comprising a compressively strained silicon germanium layer arranged on the silicon germanium layer, and the compressively strained silicon germanium layer comprising a germanium content that is less than the relaxed silicon germanium layer.

18. The method of claim 16, wherein the germanium content of the tensile strained silicon germanium layer is greater than a germanium content of the silicon germanium layer.

19. The method of claim 17, wherein the germanium content of the compressively strained silicon germanium layer is greater than a germanium content of the silicon germanium layer.

20. The method of claim 13, wherein a thickness of the silicon germanium layer of the first transistor is in a range from about 6 to about 1000 nm.