Fabrication of a sacrificial interposer test structure

• US 10,643,910 B2
• Filed: 08/17/2018
• Issued: 05/05/2020
• Est. Priority Date: 06/08/2016
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Mori, Hiroyuki, Okamoto, Keishi
• Primary Examiner(s): Gheyas, Syed I
• Application Number:
  US16/104,433
• Publication Number:
  US 20190006250A1
• Time in Patent Office: 627 Days
• CPC Class Codes: G01R 31/2637 for testing other individual devices G01R31/2608 - G01R31/2632, G01R31/27 take precedence
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/44 Testing lamps
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 Geometry or layout

Abstract

A sacrificial interposer test structure including a release layer, a dummy layer on the release layer, one or more conductive pads embedded in the dummy layer, wherein each of the one or more conductive pads has an exposed surface, and a tie layer on the dummy layer and on each exposed surface of the one or more conductive pads.

Claims

1. An interposer test structure attached to a device, comprising:

a bonding pad affixed to each of two or more interposer via contacts and each of two or more interposer lead contacts, wherein the two or more interposer via contacts and two or more interposer lead contacts are embedded in an insulator material layer;

a first interposer via in physical and electrical contact with a first interposer via contact, and a second interposer via in physical and electrical contact with a second interposer via contact of the two or more interposer via contacts;

a first lead in physical and electrical contact with a first of the two or more interposer lead contacts, and a second lead in physical and electrical contact with a second of the two or more interposer lead contacts;

two or more chip contacts, wherein one of the two or more chip contacts is in physical and electrical contact with the first interposer via and another of the two or more chip contacts is in physical and electrical contact with the second interposer via; and

an interposer lead embedded in the insulator material layer, and in physical and electrical contact with the first and second leads.

2. The interposer test structure of claim 1, wherein the interposer via contacts and interposer lead contacts each have a thickness in a range of about 5 um to about 30 um.

3. The interposer test structure of claim 1, wherein the interposer via contacts and interposer lead contacts are copper.

4. The interposer test structure of claim 1, wherein the insulator material layer is polyimide or epoxy resin.

5. The interposer test structure of claim 1, wherein the interposer vias are titanium copper (Ti/Cu).

6. The interposer test structure of claim 1, wherein the interposer vias have a diameter in the range of about 10 um to about 25 um.

7. The interposer test structure of claim 1, further comprising one or more channels in the insulator material layer, wherein the channels are filled with copper.

8. The interposer test structure of claim 7, wherein one of the one or more channels is electrically connected to one of the separate interposer vias.

9. A method of using an interposer test structure, comprising:

forming a plurality of conductive pads on a substrate;

depositing a tie layer on at least two of the plurality of conductive pads, wherein the tie layer is in electrical contact with the at least two of the plurality of conductive pads;

forming four interposer contacts in an insulator layer, wherein each of the four interposer contacts is in physical and electrical contact with the tie layer;

forming an interposer lead electrically connecting two of the four interposer contacts;

forming a separate chip contact to each of two of the four interposer contacts other than the two interposer contacts electrically connected by the interposer lead, wherein the two chip contacts, four interposer contacts, tie layer, and interposer lead form an electrical path; and

measuring the resistance across the electrical path.

10. The method of claim 9, wherein the interposer via contacts and interposer lead contacts each have a thickness in a range of about 5 um to about 30 um.

11. The method of claim 10, wherein the interposer via contacts and interposer lead contacts are copper.

12. The method of claim 11, wherein the insulator material layer is polyimide or epoxy resin.

13. The method of claim 12, further comprising forming a separate interposer via between each chip contact and one of the two interposer contacts.

14. The method of claim 13, wherein the interposer vias have a diameter in the range of about 10 um to about 25 um.

15. A method of testing an interposer, comprising:

forming an interposer on a sacrificial test structure, wherein the interposer includes a body and a plurality of electrically connected interposer contacts and chip contacts embedded in the body, where at least a portion of the electrically connected interposer contacts are in electrical contact with the sacrificial test structure, wherein the sacrificial test structure includes a conductive tie layer in contact with the interposer contacts; and

attaching at least two test probes to at least two different chip contacts on the surface of the interposer, wherein a resistance between the electrically connected interposer contacts is measured to determine if a conductive path between the electrically connected interposer contacts is open or closed.

16. The method of claim 15, wherein the sacrificial test structure includes one or more conductive pads in contact with the conductive tie layer, wherein the conductive pads form a conductive bridge between two or more interposer contacts, such that a resistance for a complete conductive path between two chip contacts can be measured.

17. The method of claim 16, wherein the sacrificial test structure includes a release layer, and a substrate in contact with the release layer, wherein the release layer couples the tie layer to the substrate.

18. The method of claim 17, further comprising discarding the interposer in response to determining the resistance for the complete conductive path between two chip contacts indicates the interposer is defective.

19. The method of claim 17, further comprising coupling the interposer to a handling structure, and separating the substrate from the sacrificial test structure at the release layer after measuring the resistance for the complete conductive path between two chip contacts.

20. The method of claim 19, wherein the release layer is titanium, and the substrate is separated from the sacrificial test structure by exposing the release layer to laser light.