Chip package interaction (CPI) back-end-of-line (BEOL) monitoring structure and method

• US 10,643,912 B2
• Filed: 07/24/2017
• Issued: 05/05/2020
• Est. Priority Date: 07/24/2017
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Pozder, Scott K., Chua, Eng Chye
• Primary Examiner(s): Hu, Shouxiang
• Application Number:
  US15/657,312
• Publication Number:
  US 20190027413A1
• Time in Patent Office: 1,016 Days
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/53295 Stacked insulating layers

Abstract

Various embodiments include monitoring structures for integrated circuits (ICs) and related monitoring methods. In some cases, a monitoring structure includes: a set of serpentine-comb structures configured to connect with a back-end-of-line (BEOL) portion of the IC, each of the serpentine-comb structures including: a chain of interconnected laterally extending wires spanning a set of metal levels in the IC; and a set of vias connecting the chain of interconnected laterally extending wires across the set of metal levels, wherein the set of vias includes at least one via spanning between each successive level of the chain of interconnected laterally extending wires, wherein the chain of interconnected laterally extending wires and the set of vias are configured to detect a chip package interface (CPI) failure in the IC.

Claims

1. A monitoring structure for the testing of an integrated circuit (IC) with a set of metal levels, the monitoring structure comprising:

a set of serpentine-comb structures configured to connect with the IC at a back-end-of-line (BEOL), wherein each of the serpentine-comb structures is disposed on a corresponding side of the set of metal levels in the IC, each of the serpentine-comb structures including;

a set of wires aligned with and parallel to the set of metal levels in the IC, each wire aligning with the corresponding one of the metal levels; and

a set of vias, wherein sub-sets of two distinct vias in the set of vias connect two successive parallel wires aligned with two metal levels of the IC, wherein the set of vias and the set of wires form a chain of interconnected wires,

wherein each sub-set of two distinct vias between two successive wires is located proximate to a same end of the two successive wires of the chain of interconnected wires,

wherein the chain of interconnected wires is configured to detect a chip package interface (CPI) failure in the IC.

2. The monitoring structure of claim 1, wherein the set of serpentine-comb structures includes a plurality of serpentine comb structures arranged in a grid, the grid sized to contact distinct areas in the BEOL portion of the IC for CPI testing.

3. The monitoring structure of claim 1, wherein the chain of interconnected wires spans levels corresponding to an entirety of the set of metal levels in the IC.

4. The monitoring structure of claim 1, wherein each of the serpentine-comb structures is configured to detect the CPI failure in the IC during a wafer-level test of the IC.

5. The monitoring structure of claim 4, wherein the wafer-level test includes a back-end-of-line (BEOL) stability indentation (BABSI) test, wherein the CPI failure is detected in response to a current flowing through at least one of the set of serpentine-comb structures deviating from an expected current.

6. A method of testing an integrated circuit (IC) with a set of metal levels for a chip package interface (CPI) failure, the method comprising:

coupling a monitoring structure to the IC at a back-end-of-line (BEOL), the monitoring structure having;

a set of serpentine-comb structures configured to connect with the IC at a back-end-of-line (BEOL), wherein each of the serpentine-comb structures is disposed on a corresponding side of the set of metal levels in the IC, each of the serpentine-comb structures including;

a set of wires aligned with and parallel to the set of metal levels in the IC, each wire aligning with the corresponding one of the metal levels; and

a set of vias, wherein sub-sets of two distinct vias in the set of vias connect two successive parallel wires aligned with two metal levels of the IC, wherein the set of vias and the set of wires form a chain of interconnected wires,

wherein each sub-set of two distinct vias between two successive wires is located proximate to a same end of the two successive wires of the chain of interconnected wires,

wherein the chain of interconnected wires is configured to detect the chip package interface (CPI) failure in the IC;

initiating a test current through the IC and the monitoring structure;

measuring the test current at the monitoring structure; and

indicating the CPI failure is likely in response to the current measured at the monitoring structure deviating from an expected current at the monitoring structure.

7. The method of claim 6, wherein the chain of interconnected wires and the set of vias are configured to aid in detecting the chip package interface (CPI) failure in the IC.

8. The method of claim 6, wherein the set of serpentine-comb structures includes a plurality of serpentine comb structures arranged in a grid, the grid sized to contact distinct areas in the BEOL portion of the IC during the CPI testing.

9. The method of claim 6, wherein each of the serpentine-comb structures is configured to detect the CPI failure in the IC during the CPI testing.

10. The method of claim 9, wherein the wafer-level test includes a back-end-of-line (BEOL) stability indentation (BABSI) test, wherein the CPI failure is detected in response to a current flowing through at least one of the set of serpentine-comb structures deviating from an expected current.

11. A monitoring structure for the testing an integrated circuit (IC) with a set of metal levels, the monitoring structure comprising:

a plurality of serpentine-comb structures arranged in a grid, each of the serpentine-comb structures configured to configured to connect with the IC at a back-end-of-line (BEOL), wherein each of the serpentine-comb structures is disposed on a corresponding side of the set of metal levels in the IC, each of the serpentine-comb structures including;

a set of wires aligned with and parallel to the set of metal levels in the IC, each wire aligning with the corresponding one of the metal levels; and

a set of vias, wherein sub-sets of two distinct vias in the set of vias connect two successive parallel wires aligned with two metal levels of the IC, wherein the set of vias and the set of wires form a chain of interconnected wires,

wherein each sub-set of two distinct vias between two successive wires is located proximate to a same end of the two successive wires of the chain of interconnected wires,

wherein the chain of interconnected wires is configured to detect a chip package interface (CPI) failure in the IC.

12. The monitoring structure of claim 11, wherein the chain of interconnected wires spans levels corresponding to an entirety of the set of metal levels in the IC.

13. The monitoring structure of claim 11, wherein each of the serpentine-comb structures is configured to detect the CPI failure in the IC during a wafer-level test of the IC.

14. The monitoring structure of claim 13, wherein the wafer-level test includes a back-end-of-line (BEOL) stability indentation (BABSI) test, wherein the CPI failure is detected in response to a current flowing through at least one of the set of serpentine-comb structures deviating from an expected current.