Fan-out semiconductor package

• US 10,643,919 B2
• Filed: 08/07/2018
• Issued: 05/05/2020
• Est. Priority Date: 11/08/2017
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Oh, Hwa Sub, Lee, Doo Hwan
• Primary Examiner(s): Nguyen, Thinh T
• Application Number:
  US16/057,023
• Publication Number:
  US 20190139853A1
• Time in Patent Office: 637 Days
• Field of Search: 257668, 257675, 257687, 438123, 438106, 438121
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/83191 wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/16 Fillings or auxiliary members in containers or encapsulations, e.g. centering rings H01L23/42, H01L23/552 take precedence
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/3736 Metallic materials H01L23/3732, H01L23/3733, H01L23/3735, H01L23/3737, H01L23/3738 take precedence
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/50 : for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A fan-out semiconductor package includes a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface, a heat dissipation member attached to the inactive surface of the semiconductor chip, an encapsulant covering at least portions of each of the semiconductor chip and the heat dissipation member, and a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads. The heat dissipation member has a thickness greater than that of the semiconductor chip.

Claims

1. A fan-out semiconductor package comprising:

a semiconductor chip comprising;

an active surface comprising connection pads disposed thereon; and

an inactive surface opposing the active surface; and

a first side surface extending substantially perpendicular to the active surface and the inactive surface of the semiconductor chip;

a heat dissipation layer attached to the inactive surface of the semiconductor chip and comprising a second side surface extending substantially perpendicular to the active surface and the inactive surface of the semiconductor chip;

an encapsulant covering at least portions of each of the semiconductor chip and the heat dissipation layer; and

a connection layer disposed on the active surface of the semiconductor chip and comprising a redistribution layer electrically connected to the connection pads,

wherein the heat dissipation layer has a thickness greater than that of the semiconductor chip, and

wherein the first side surface of the semiconductor chip and the second side surface of the heat dissipation layer are coplanar.

2. The fan-out semiconductor package of claim 1, wherein the thickness of the semiconductor chip is 0.4 to 0.6 times the thickness of the heat dissipation layer.

3. The fan-out semiconductor package of claim 1, wherein the heat dissipation layer is attached to the inactive surface of the semiconductor chip by an adhesive film.

4. The fan-out semiconductor package of claim 3, wherein the adhesive film comprises a die attach film (DAF) having a thickness of 1 μ

m to 10 μ

m.

5. The fan-out semiconductor package of claim 1, wherein the heat dissipation layer comprises a copper (Cu) lump.

6. The fan-out semiconductor package of claim 5, wherein an organic coating layer is formed on the Cu lump.

7. The fan-out semiconductor package of claim 6, wherein the organic coating layer comprises a silane coating layer.

8. The fan-out semiconductor package of claim 1, wherein the encapsulant comprises an insulating resin and an inorganic filler, and

a content of the inorganic filler in the encapsulant is 60 wt % to 80 wt %.

9. The fan-out semiconductor package of claim 1, further comprising:

a heat dissipation pattern layer disposed on the encapsulant; and

heat dissipation vias penetrating through at least portions of the encapsulant and connecting the heat dissipation pattern layer and the heat dissipation layer to each other.

11. The fan-out semiconductor package of claim 1, further comprising a core member comprising a through-hole,

wherein;

the semiconductor chip and the heat dissipation layer are disposed in the through-hole, and

the encapsulant covers at least portions of the core member, the semiconductor chip, and the heat dissipation layer, and fills at least portions of the through-hole.

12. The fan-out semiconductor package of claim 11, wherein:

the core member comprises a plurality of wiring layers, and

the plurality of wiring layers of the core member are electrically connected to the connection pads of the semiconductor chip through the redistribution layer of the connection layer.

13. The fan-out semiconductor package of claim 12, further comprising:

a backside wiring layer disposed on the encapsulant; and

backside vias penetrating through at least portions of the encapsulant and electrically connecting the backside wiring layer and an uppermost wiring layer of the plurality of wiring layers of the core member to each other.

15. The fan-out semiconductor package of claim 12, wherein the core member further comprises:

a first insulating layer in contact with the connection layer;

a first wiring layer embedded in the first insulating layer and in contact with the connection layer;

a second wiring layer disposed on a second surface of the first insulating layer opposing a first surface of the first insulating layer in which the first wiring layer is embedded;

a second insulating layer disposed on the first insulating layer and covering the second wiring layer; and

a third wiring layer disposed on the second insulating layer, and

the first wiring layer, the second wiring layer and the third wiring layer are electrically connected to the connection pads of the semiconductor chip.

16. The fan-out semiconductor package of claim 15, wherein the core member further comprises:

a third insulating layer disposed on the second insulating layer and covering the third wiring layer, and

a fourth wiring layer disposed on the third insulating layer, and

the first to fourth wiring layers are electrically connected to the connection pads of the semiconductor chip.

17. The fan-out semiconductor package of claim 15, wherein a lower surface of the first wiring layer and a lower surface of the first insulating layer have a step portion provided therebetween.

18. The fan-out semiconductor package of claim 12, wherein the core member comprises:

a first insulating layer;

a first wiring layer disposed on a lower surface of the first insulating layer; and

a second wiring layer disposed on an upper surface of the first insulating layer, and

the first wiring layer and the second wiring layer are electrically connected to the connection pads of the semiconductor chip.

19. The fan-out semiconductor package of claim 18, wherein the core member further comprises:

a second insulating layer disposed on the lower surface of the first insulating layer and covering the first wiring layer;

a third wiring layer disposed on a lower surface of the second insulating layer;

a third insulating layer disposed on the upper surface of the first insulating layer and covering the second wiring layer; and

a fourth wiring layer disposed on an upper surface of the third insulating layer, and

the first to fourth wiring layers are electrically connected to the connection pads of the semiconductor chip.

20. The fan-out semiconductor package of claim 19, wherein the first insulating layer has a thickness greater than that of each of the second insulating layer and the third insulating layer.

10. A fan-out semiconductor package comprising:

a semiconductor chip comprising;

an active surface comprising connection pads disposed thereon; and

an inactive surface opposing the active surface;

a heat dissipation layer attached to the inactive surface of the semiconductor chip;

an encapsulant covering at least portions of each of the semiconductor chip and the heat dissipation layer;

a connection layer disposed on the active surface of the semiconductor chip and comprising a redistribution layer electrically connected to the connection pads;

a heat dissipation pattern layer disposed on the encapsulant;

a reinforcing layer disposed between the encapsulant and the heat dissipation pattern layer; and

a cover layer disposed on the reinforcing layer and covering at least portions of the heat dissipation pattern layer,

wherein the heat dissipation layer has a thickness greater than that of the semiconductor chip, and

wherein the reinforcing layer has an elastic modulus greater than that of each of the encapsulant and the cover layer.

14. A fan-out semiconductor package comprising

a semiconductor chip comprising:

an active surface comprising connection pads disposed thereon; and

an inactive surface opposing the active surface;

a heat dissipation layer attached to the inactive surface of the semiconductor chip;

an encapsulant covering at least portions of each of the semiconductor chip and the heat dissipation layer;

a connection layer disposed on the active surface of the semiconductor chip and comprising a redistribution layer electrically connected to the connection pads;

a core member comprising;

a through-hole; and

a plurality of wiring layers;

a backside wiring layer disposed on the encapsulant;

backside vias penetrating through at least portions of the encapsulant and electrically connecting the backside wiring layer and an uppermost wiring layer of the plurality of wiring layers of the core member to each other;

a reinforcing layer disposed between the encapsulant and the backside wiring layer; and

a cover layer disposed on the reinforcing layer and covering at least portions of the backside wiring layer,

wherein the heat dissipation layer has a thickness greater than that of the semiconductor chip, and

wherein the reinforcing layer has an elastic modulus greater than that of each of the encapsulant and the cover layer.