Lid for semiconductor electronic package

• US 10,643,920 B1
• Filed: 12/20/2017
• Issued: 05/05/2020
• Est. Priority Date: 03/24/2017
• Status: Active Grant

• Current Assignee: Juniper Networks Incorporated
• Original Assignee: Juniper Networks Incorporated
• Inventors: Yatskov, Alexander I., Ganguly, Gautam
• Primary Examiner(s): Smith, Zandra V
• Assistant Examiner(s): Joy, Jeremy J
• Application Number:
  US15/848,627
• Time in Patent Office: 867 Days
• CPC Class Codes: H01L 21/4878 Mechanical treatment, e.g. deforming
• CPC Class Codes: H01L 21/4882 Assembly of heatsink parts
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29193 with a principal constituent of the material being a solid not provided for in groups H01L2224/291 - H01L2224/29191, e.g. allotropes of carbon, fullerene, graphite, carbon-nanotubes, diamond
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 23/04 characterised by the shape of the container or parts, e.g. caps, walls
• CPC Class Codes: H01L 23/053 the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
• CPC Class Codes: H01L 23/24 solid or gel at the normal operating temperature of the device H01L23/3135 takes precedence
• CPC Class Codes: H01L 23/3672 Foil-like cooling fins or heat sinks being part of lead-frames H01L23/49568
• CPC Class Codes: H01L 23/3675 characterised by the shape of the housing
• CPC Class Codes: H01L 23/3736 Metallic materials H01L23/3732, H01L23/3733, H01L23/3735, H01L23/3737, H01L23/3738 take precedence
• CPC Class Codes: H01L 23/3737 Organic materials with or without a thermoconductive filler
• CPC Class Codes: H01L 23/42 Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 24/32 of an individual layer connector
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0635 : Acrylic polymer
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/069 : Polyurethane
• CPC Class Codes: H01L 2924/0715 : Polysiloxane
• CPC Class Codes: H01L 2924/16151 : Cap comprising an aperture, e.g. for pressure control, encapsulation
• CPC Class Codes: H01L 2924/16235 : Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
• CPC Class Codes: H01L 2924/16251 : Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

Techniques are described to limit heat transfer from a first electronic component to a second electronic such as by having an aperture in a lid over the second electronic component to form a gap in the conductance of heat from the first electronic component to the second electronic component. A semiconductor electronic package includes a substrate, a first electronic component that is of a first type and that is mounted along a surface of the substrate, a second electronic component that is of a second type different than the first type and that is mounted along the surface of the substrate, and a metallic component that is positioned over the first electronic component and that has an aperture through which the second electronic component is exposed.

Claims

1. A semiconductor electronic package, comprising:

a substrate;

a first electronic component that is of a first type and that is mounted along a surface of the substrate, wherein the first electronic component includes at least one integrated circuit die;

a second electronic component that is of a second type different than the first type, wherein the second electronic component is mounted along the surface of the substrate and is spaced apart along the surface of the substrate from the first electronic component, wherein the second electronic component includes at least one memory element; and

a metallic component that is positioned over the first electronic component and that has an aperture through which the second electronic component is exposed, wherein the aperture has a cross-sectional area that is less than or equal to a footprint of the first electronic component on the substrate.

2. The package of claim 1, wherein the substrate is a silicon interposer.

3. The semiconductor electronic package of claim 1, wherein the metallic component is a lid configured as a heat sink for the first electronic component which has a thermal operating limit greater than the second electronic component.

4. The semiconductor electronic package of claim 1, further comprising a thermal interface material positioned between and in contact with the metallic component and the first electronic component.

5. The semiconductor electronic package of claim 1, further comprising a thermal interface material positioned over a surface of the second electronic component and exposed though the aperture.

6. The semiconductor electronic package of claim 1, wherein the cross-sectional area is greater than or equal to a footprint of the second electronic component on the substrate.

7. The semiconductor electronic package of claim 1, wherein the metallic component is positioned over and coupled to a surface of the first electronic component, and wherein a surface of the second electronic component is exposed through the aperture.

8. A method, comprising:

mounting a metallic component to a semiconductor electronic package, that includes a first electronic component and a second electronic component that is of a type different than the first electronic component, so that the first electronic component is covered by the metallic component and the second electronic component is exposed through an aperture of the metallic component, wherein the first electronic component and the second electronic component are mounted along a surface of a substrate of the semiconductor electronic package, wherein the first electronic component is spaced apart along the surface of the substrate from the second electronic component, wherein the first electronic component includes at least one integrated circuit die, and wherein the second electronic component includes at least one memory element; and

machining the aperture into the metallic component so that the aperture has a cross-sectional area less than or equal to a footprint of the first electronic component on the substrate of the semiconductor electronic package.

9. The method of claim 8, wherein machining the aperture comprises machining the aperture into the metallic component so that the cross-sectional area is greater than or equal to a footprint of the second electronic component on the substrate of the semiconductor electronic package.

10. The method of claim 8, further comprising mounting the first electronic component and the second electronic component adjacent along a surface of the substrate of the semiconductor electronic package.

11. The method of claim 8, further comprising depositing a thermal interface material between and in contact with the metallic component and the first electronic component.

12. The method of claim 8, further comprising depositing a thermal interface material to a surface of the second electronic component that is exposed though the aperture.

13. A semiconductor electronic package, comprising:

a first electronic component that is of a first type;

a second electronic component that is of a second type different than the first type, wherein the first electronic component and the second electronic component are mounted along a surface of a substrate of the semiconductor electronic package and wherein the first electronic component is spaced apart along the surface of the substrate from the second electronic component;

a metallic lid that is positioned to cover the first electronic component, the metallic lid having an aperture to expose the second electronic component, wherein the aperture has a cross-sectional area that is less than or equal to a footprint of the first electronic component on the substrate of the semiconductor electronic package; and

a first thermal interface material positioned between and in contact with the metallic lid and the first electronic component.

14. The semiconductor electronic package of claim 13, wherein the cross-sectional area is greater than or equal to a footprint of the second electronic component on the substrate of the semiconductor electronic package.

15. The semiconductor electronic package of claim 13, further comprising and a second thermal interface material positioned over a surface of the second electronic component and exposed though the aperture.

16. A semiconductor electronic package, comprising:

a substrate;

a first electronic component that is of a first type and that is mounted along a surface of the substrate, wherein the first electronic component comprises at least one integrated circuit die;

a plurality of second electronic components that are of a second type different than the first type, wherein each of the plurality of second electronic components is mounted along the surface of the substrate and is spaced apart along the surface of the substrate from the first electronic component and wherein each of the second electronic components comprises at least one memory element;

a metallic component that is positioned over the first electronic component and that has an aperture through which the plurality of second electronic components are exposed, wherein the aperture has a cross-sectional area that is less than or equal to a footprint of the first electronic component on the substrate;

a first heat sink coupled to the metallic component to dissipate heat generated by the first electronic component away from the first electronic component; and

a second heat sink, separate from the first heat sink, coupled to the plurality of second electronic components to dissipate heat generated by the plurality of second electronic components away from the plurality of second electronic components.